target/linux/brcm2708/patches-4.9/0170-drm-vc4-Add-support-for-the-VEC-Video-Encoder-IP.patch

   1 From d79cd118969fb3ad714feb834eefdddcc4348673 Mon Sep 17 00:00:00 2001
   2 From: Boris Brezillon <boris.brezillon@free-electrons.com>
   3 Date: Fri, 2 Dec 2016 14:48:10 +0100
   4 Subject: [PATCH] drm/vc4: Add support for the VEC (Video Encoder) IP
   5
   6 The VEC IP is a TV DAC, providing support for PAL and NTSC standards.
   7
   8 Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
   9 Signed-off-by: Eric Anholt <eric@anholt.net>
  10 (cherry picked from commit e4b81f8c74c82dbc0cb0e5ceb5ef9b713b325fc9)
  11 ---
  12  drivers/gpu/drm/vc4/Makefile      |   1 +
  13  drivers/gpu/drm/vc4/vc4_debugfs.c |   1 +
  14  drivers/gpu/drm/vc4/vc4_drv.c     |   1 +
  15  drivers/gpu/drm/vc4/vc4_drv.h     |   5 +
  16  drivers/gpu/drm/vc4/vc4_vec.c     | 657 ++++++++++++++++++++++++++++++++++++++
  17  5 files changed, 665 insertions(+)
  18  create mode 100644 drivers/gpu/drm/vc4/vc4_vec.c
  19
  20 --- a/drivers/gpu/drm/vc4/Makefile
  21 +++ b/drivers/gpu/drm/vc4/Makefile
  22 @@ -12,6 +12,7 @@ vc4-y := \
  23         vc4_kms.o \
  24         vc4_gem.o \
  25         vc4_hdmi.o \
  26 +       vc4_vec.o \
  27         vc4_hvs.o \
  28         vc4_irq.o \
  29         vc4_plane.o \
  30 --- a/drivers/gpu/drm/vc4/vc4_debugfs.c
  31 +++ b/drivers/gpu/drm/vc4/vc4_debugfs.c
  32 @@ -19,6 +19,7 @@ static const struct drm_info_list vc4_de
  33         {"bo_stats", vc4_bo_stats_debugfs, 0},
  34         {"dpi_regs", vc4_dpi_debugfs_regs, 0},
  35         {"hdmi_regs", vc4_hdmi_debugfs_regs, 0},
  36 +       {"vec_regs", vc4_vec_debugfs_regs, 0},
  37         {"hvs_regs", vc4_hvs_debugfs_regs, 0},
  38         {"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0},
  39         {"crtc1_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)1},
  40 --- a/drivers/gpu/drm/vc4/vc4_drv.c
  41 +++ b/drivers/gpu/drm/vc4/vc4_drv.c
  42 @@ -294,6 +294,7 @@ static const struct component_master_ops
  43
  44  static struct platform_driver *const component_drivers[] = {
  45         &vc4_hdmi_driver,
  46 +       &vc4_vec_driver,
  47         &vc4_dpi_driver,
  48         &vc4_hvs_driver,
  49         &vc4_crtc_driver,
  50 --- a/drivers/gpu/drm/vc4/vc4_drv.h
  51 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
  52 @@ -20,6 +20,7 @@ struct vc4_dev {
  53         struct vc4_crtc *crtc[3];
  54         struct vc4_v3d *v3d;
  55         struct vc4_dpi *dpi;
  56 +       struct vc4_vec *vec;
  57
  58         struct drm_fbdev_cma *fbdev;
  59
  60 @@ -494,6 +495,10 @@ int vc4_queue_seqno_cb(struct drm_device
  61  extern struct platform_driver vc4_hdmi_driver;
  62  int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
  63
  64 +/* vc4_hdmi.c */
  65 +extern struct platform_driver vc4_vec_driver;
  66 +int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
  67 +
  68  /* vc4_irq.c */
  69  irqreturn_t vc4_irq(int irq, void *arg);
  70  void vc4_irq_preinstall(struct drm_device *dev);
  71 --- /dev/null
  72 +++ b/drivers/gpu/drm/vc4/vc4_vec.c
  73 @@ -0,0 +1,657 @@
  74 +/*
  75 + * Copyright (C) 2016 Broadcom
  76 + *
  77 + * This program is free software; you can redistribute it and/or modify it
  78 + * under the terms of the GNU General Public License version 2 as published by
  79 + * the Free Software Foundation.
  80 + *
  81 + * This program is distributed in the hope that it will be useful, but WITHOUT
  82 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  83 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  84 + * more details.
  85 + *
  86 + * You should have received a copy of the GNU General Public License along with
  87 + * this program.  If not, see <http://www.gnu.org/licenses/>.
  88 + */
  89 +
  90 +/**
  91 + * DOC: VC4 SDTV module
  92 + */
  93 +
  94 +#include <drm/drm_atomic_helper.h>
  95 +#include <drm/drm_crtc_helper.h>
  96 +#include <drm/drm_edid.h>
  97 +#include <drm/drm_panel.h>
  98 +#include <linux/clk.h>
  99 +#include <linux/component.h>
 100 +#include <linux/of_graph.h>
 101 +#include <linux/of_platform.h>
 102 +#include <linux/pm_runtime.h>
 103 +
 104 +#include "vc4_drv.h"
 105 +#include "vc4_regs.h"
 106 +
 107 +/* WSE Registers */
 108 +#define VEC_WSE_RESET                  0xc0
 109 +
 110 +#define VEC_WSE_CONTROL                        0xc4
 111 +#define VEC_WSE_WSS_ENABLE             BIT(7)
 112 +
 113 +#define VEC_WSE_WSS_DATA               0xc8
 114 +#define VEC_WSE_VPS_DATA1              0xcc
 115 +#define VEC_WSE_VPS_CONTROL            0xd0
 116 +
 117 +/* VEC Registers */
 118 +#define VEC_REVID                      0x100
 119 +
 120 +#define VEC_CONFIG0                    0x104
 121 +#define VEC_CONFIG0_YDEL_MASK          GENMASK(28, 26)
 122 +#define VEC_CONFIG0_YDEL(x)            ((x) << 26)
 123 +#define VEC_CONFIG0_CDEL_MASK          GENMASK(25, 24)
 124 +#define VEC_CONFIG0_CDEL(x)            ((x) << 24)
 125 +#define VEC_CONFIG0_PBPR_FIL           BIT(18)
 126 +#define VEC_CONFIG0_CHROMA_GAIN_MASK   GENMASK(17, 16)
 127 +#define VEC_CONFIG0_CHROMA_GAIN_UNITY  (0 << 16)
 128 +#define VEC_CONFIG0_CHROMA_GAIN_1_32   (1 << 16)
 129 +#define VEC_CONFIG0_CHROMA_GAIN_1_16   (2 << 16)
 130 +#define VEC_CONFIG0_CHROMA_GAIN_1_8    (3 << 16)
 131 +#define VEC_CONFIG0_CBURST_GAIN_MASK   GENMASK(14, 13)
 132 +#define VEC_CONFIG0_CBURST_GAIN_UNITY  (0 << 13)
 133 +#define VEC_CONFIG0_CBURST_GAIN_1_128  (1 << 13)
 134 +#define VEC_CONFIG0_CBURST_GAIN_1_64   (2 << 13)
 135 +#define VEC_CONFIG0_CBURST_GAIN_1_32   (3 << 13)
 136 +#define VEC_CONFIG0_CHRBW1             BIT(11)
 137 +#define VEC_CONFIG0_CHRBW0             BIT(10)
 138 +#define VEC_CONFIG0_SYNCDIS            BIT(9)
 139 +#define VEC_CONFIG0_BURDIS             BIT(8)
 140 +#define VEC_CONFIG0_CHRDIS             BIT(7)
 141 +#define VEC_CONFIG0_PDEN               BIT(6)
 142 +#define VEC_CONFIG0_YCDELAY            BIT(4)
 143 +#define VEC_CONFIG0_RAMPEN             BIT(2)
 144 +#define VEC_CONFIG0_YCDIS              BIT(2)
 145 +#define VEC_CONFIG0_STD_MASK           GENMASK(1, 0)
 146 +#define VEC_CONFIG0_NTSC_STD           0
 147 +#define VEC_CONFIG0_PAL_BDGHI_STD      1
 148 +#define VEC_CONFIG0_PAL_N_STD          3
 149 +
 150 +#define VEC_SCHPH                      0x108
 151 +#define VEC_SOFT_RESET                 0x10c
 152 +#define VEC_CLMP0_START                        0x144
 153 +#define VEC_CLMP0_END                  0x148
 154 +#define VEC_FREQ3_2                    0x180
 155 +#define VEC_FREQ1_0                    0x184
 156 +
 157 +#define VEC_CONFIG1                    0x188
 158 +#define VEC_CONFIG_VEC_RESYNC_OFF      BIT(18)
 159 +#define VEC_CONFIG_RGB219              BIT(17)
 160 +#define VEC_CONFIG_CBAR_EN             BIT(16)
 161 +#define VEC_CONFIG_TC_OBB              BIT(15)
 162 +#define VEC_CONFIG1_OUTPUT_MODE_MASK   GENMASK(12, 10)
 163 +#define VEC_CONFIG1_C_Y_CVBS           (0 << 10)
 164 +#define VEC_CONFIG1_CVBS_Y_C           (1 << 10)
 165 +#define VEC_CONFIG1_PR_Y_PB            (2 << 10)
 166 +#define VEC_CONFIG1_RGB                        (4 << 10)
 167 +#define VEC_CONFIG1_Y_C_CVBS           (5 << 10)
 168 +#define VEC_CONFIG1_C_CVBS_Y           (6 << 10)
 169 +#define VEC_CONFIG1_C_CVBS_CVBS                (7 << 10)
 170 +#define VEC_CONFIG1_DIS_CHR            BIT(9)
 171 +#define VEC_CONFIG1_DIS_LUMA           BIT(8)
 172 +#define VEC_CONFIG1_YCBCR_IN           BIT(6)
 173 +#define VEC_CONFIG1_DITHER_TYPE_LFSR   0
 174 +#define VEC_CONFIG1_DITHER_TYPE_COUNTER        BIT(5)
 175 +#define VEC_CONFIG1_DITHER_EN          BIT(4)
 176 +#define VEC_CONFIG1_CYDELAY            BIT(3)
 177 +#define VEC_CONFIG1_LUMADIS            BIT(2)
 178 +#define VEC_CONFIG1_COMPDIS            BIT(1)
 179 +#define VEC_CONFIG1_CUSTOM_FREQ                BIT(0)
 180 +
 181 +#define VEC_CONFIG2                    0x18c
 182 +#define VEC_CONFIG2_PROG_SCAN          BIT(15)
 183 +#define VEC_CONFIG2_SYNC_ADJ_MASK      GENMASK(14, 12)
 184 +#define VEC_CONFIG2_SYNC_ADJ(x)                (((x) / 2) << 12)
 185 +#define VEC_CONFIG2_PBPR_EN            BIT(10)
 186 +#define VEC_CONFIG2_UV_DIG_DIS         BIT(6)
 187 +#define VEC_CONFIG2_RGB_DIG_DIS                BIT(5)
 188 +#define VEC_CONFIG2_TMUX_MASK          GENMASK(3, 2)
 189 +#define VEC_CONFIG2_TMUX_DRIVE0                (0 << 2)
 190 +#define VEC_CONFIG2_TMUX_RG_COMP       (1 << 2)
 191 +#define VEC_CONFIG2_TMUX_UV_YC         (2 << 2)
 192 +#define VEC_CONFIG2_TMUX_SYNC_YC       (3 << 2)
 193 +
 194 +#define VEC_INTERRUPT_CONTROL          0x190
 195 +#define VEC_INTERRUPT_STATUS           0x194
 196 +#define VEC_FCW_SECAM_B                        0x198
 197 +#define VEC_SECAM_GAIN_VAL             0x19c
 198 +
 199 +#define VEC_CONFIG3                    0x1a0
 200 +#define VEC_CONFIG3_HORIZ_LEN_STD      (0 << 0)
 201 +#define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF        (1 << 0)
 202 +#define VEC_CONFIG3_SHAPE_NON_LINEAR   BIT(1)
 203 +
 204 +#define VEC_STATUS0                    0x200
 205 +#define VEC_MASK0                      0x204
 206 +
 207 +#define VEC_CFG                                0x208
 208 +#define VEC_CFG_SG_MODE_MASK           GENMASK(6, 5)
 209 +#define VEC_CFG_SG_MODE(x)             ((x) << 5)
 210 +#define VEC_CFG_SG_EN                  BIT(4)
 211 +#define VEC_CFG_VEC_EN                 BIT(3)
 212 +#define VEC_CFG_MB_EN                  BIT(2)
 213 +#define VEC_CFG_ENABLE                 BIT(1)
 214 +#define VEC_CFG_TB_EN                  BIT(0)
 215 +
 216 +#define VEC_DAC_TEST                   0x20c
 217 +
 218 +#define VEC_DAC_CONFIG                 0x210
 219 +#define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x)        ((x) << 24)
 220 +#define VEC_DAC_CONFIG_DRIVER_CTRL(x)  ((x) << 16)
 221 +#define VEC_DAC_CONFIG_DAC_CTRL(x)     (x)
 222 +
 223 +#define VEC_DAC_MISC                   0x214
 224 +#define VEC_DAC_MISC_VCD_CTRL_MASK     GENMASK(31, 16)
 225 +#define VEC_DAC_MISC_VCD_CTRL(x)       ((x) << 16)
 226 +#define VEC_DAC_MISC_VID_ACT           BIT(8)
 227 +#define VEC_DAC_MISC_VCD_PWRDN         BIT(6)
 228 +#define VEC_DAC_MISC_BIAS_PWRDN                BIT(5)
 229 +#define VEC_DAC_MISC_DAC_PWRDN         BIT(2)
 230 +#define VEC_DAC_MISC_LDO_PWRDN         BIT(1)
 231 +#define VEC_DAC_MISC_DAC_RST_N         BIT(0)
 232 +
 233 +
 234 +/* General VEC hardware state. */
 235 +struct vc4_vec {
 236 +       struct platform_device *pdev;
 237 +
 238 +       struct drm_encoder *encoder;
 239 +       struct drm_connector *connector;
 240 +
 241 +       void __iomem *regs;
 242 +
 243 +       struct clk *clock;
 244 +
 245 +       const struct vc4_vec_tv_mode *tv_mode;
 246 +};
 247 +
 248 +#define VEC_READ(offset) readl(vec->regs + (offset))
 249 +#define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
 250 +
 251 +/* VC4 VEC encoder KMS struct */
 252 +struct vc4_vec_encoder {
 253 +       struct vc4_encoder base;
 254 +       struct vc4_vec *vec;
 255 +};
 256 +
 257 +static inline struct vc4_vec_encoder *
 258 +to_vc4_vec_encoder(struct drm_encoder *encoder)
 259 +{
 260 +       return container_of(encoder, struct vc4_vec_encoder, base.base);
 261 +}
 262 +
 263 +/* VC4 VEC connector KMS struct */
 264 +struct vc4_vec_connector {
 265 +       struct drm_connector base;
 266 +       struct vc4_vec *vec;
 267 +
 268 +       /* Since the connector is attached to just the one encoder,
 269 +        * this is the reference to it so we can do the best_encoder()
 270 +        * hook.
 271 +        */
 272 +       struct drm_encoder *encoder;
 273 +};
 274 +
 275 +static inline struct vc4_vec_connector *
 276 +to_vc4_vec_connector(struct drm_connector *connector)
 277 +{
 278 +       return container_of(connector, struct vc4_vec_connector, base);
 279 +}
 280 +
 281 +enum vc4_vec_tv_mode_id {
 282 +       VC4_VEC_TV_MODE_NTSC,
 283 +       VC4_VEC_TV_MODE_NTSC_J,
 284 +       VC4_VEC_TV_MODE_PAL,
 285 +       VC4_VEC_TV_MODE_PAL_M,
 286 +};
 287 +
 288 +struct vc4_vec_tv_mode {
 289 +       const struct drm_display_mode *mode;
 290 +       void (*mode_set)(struct vc4_vec *vec);
 291 +};
 292 +
 293 +#define VEC_REG(reg) { reg, #reg }
 294 +static const struct {
 295 +       u32 reg;
 296 +       const char *name;
 297 +} vec_regs[] = {
 298 +       VEC_REG(VEC_WSE_CONTROL),
 299 +       VEC_REG(VEC_WSE_WSS_DATA),
 300 +       VEC_REG(VEC_WSE_VPS_DATA1),
 301 +       VEC_REG(VEC_WSE_VPS_CONTROL),
 302 +       VEC_REG(VEC_REVID),
 303 +       VEC_REG(VEC_CONFIG0),
 304 +       VEC_REG(VEC_SCHPH),
 305 +       VEC_REG(VEC_CLMP0_START),
 306 +       VEC_REG(VEC_CLMP0_END),
 307 +       VEC_REG(VEC_FREQ3_2),
 308 +       VEC_REG(VEC_FREQ1_0),
 309 +       VEC_REG(VEC_CONFIG1),
 310 +       VEC_REG(VEC_CONFIG2),
 311 +       VEC_REG(VEC_INTERRUPT_CONTROL),
 312 +       VEC_REG(VEC_INTERRUPT_STATUS),
 313 +       VEC_REG(VEC_FCW_SECAM_B),
 314 +       VEC_REG(VEC_SECAM_GAIN_VAL),
 315 +       VEC_REG(VEC_CONFIG3),
 316 +       VEC_REG(VEC_STATUS0),
 317 +       VEC_REG(VEC_MASK0),
 318 +       VEC_REG(VEC_CFG),
 319 +       VEC_REG(VEC_DAC_TEST),
 320 +       VEC_REG(VEC_DAC_CONFIG),
 321 +       VEC_REG(VEC_DAC_MISC),
 322 +};
 323 +
 324 +#ifdef CONFIG_DEBUG_FS
 325 +int vc4_vec_debugfs_regs(struct seq_file *m, void *unused)
 326 +{
 327 +       struct drm_info_node *node = (struct drm_info_node *)m->private;
 328 +       struct drm_device *dev = node->minor->dev;
 329 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
 330 +       struct vc4_vec *vec = vc4->vec;
 331 +       int i;
 332 +
 333 +       if (!vec)
 334 +               return 0;
 335 +
 336 +       for (i = 0; i < ARRAY_SIZE(vec_regs); i++) {
 337 +               seq_printf(m, "%s (0x%04x): 0x%08x\n",
 338 +                          vec_regs[i].name, vec_regs[i].reg,
 339 +                          VEC_READ(vec_regs[i].reg));
 340 +       }
 341 +
 342 +       return 0;
 343 +}
 344 +#endif
 345 +
 346 +static void vc4_vec_ntsc_mode_set(struct vc4_vec *vec)
 347 +{
 348 +       VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN);
 349 +       VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
 350 +}
 351 +
 352 +static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec)
 353 +{
 354 +       VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD);
 355 +       VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
 356 +}
 357 +
 358 +static const struct drm_display_mode ntsc_mode = {
 359 +       DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
 360 +                720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
 361 +                480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0,
 362 +                DRM_MODE_FLAG_INTERLACE)
 363 +};
 364 +
 365 +static void vc4_vec_pal_mode_set(struct vc4_vec *vec)
 366 +{
 367 +       VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
 368 +       VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
 369 +}
 370 +
 371 +static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec)
 372 +{
 373 +       VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
 374 +       VEC_WRITE(VEC_CONFIG1,
 375 +                 VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ);
 376 +       VEC_WRITE(VEC_FREQ3_2, 0x223b);
 377 +       VEC_WRITE(VEC_FREQ1_0, 0x61d1);
 378 +}
 379 +
 380 +static const struct drm_display_mode pal_mode = {
 381 +       DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
 382 +                720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
 383 +                576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0,
 384 +                DRM_MODE_FLAG_INTERLACE)
 385 +};
 386 +
 387 +static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
 388 +       [VC4_VEC_TV_MODE_NTSC] = {
 389 +               .mode = &ntsc_mode,
 390 +               .mode_set = vc4_vec_ntsc_mode_set,
 391 +       },
 392 +       [VC4_VEC_TV_MODE_NTSC_J] = {
 393 +               .mode = &ntsc_mode,
 394 +               .mode_set = vc4_vec_ntsc_j_mode_set,
 395 +       },
 396 +       [VC4_VEC_TV_MODE_PAL] = {
 397 +               .mode = &pal_mode,
 398 +               .mode_set = vc4_vec_pal_mode_set,
 399 +       },
 400 +       [VC4_VEC_TV_MODE_PAL_M] = {
 401 +               .mode = &pal_mode,
 402 +               .mode_set = vc4_vec_pal_m_mode_set,
 403 +       },
 404 +};
 405 +
 406 +static enum drm_connector_status
 407 +vc4_vec_connector_detect(struct drm_connector *connector, bool force)
 408 +{
 409 +       return connector_status_unknown;
 410 +}
 411 +
 412 +static void vc4_vec_connector_destroy(struct drm_connector *connector)
 413 +{
 414 +       drm_connector_unregister(connector);
 415 +       drm_connector_cleanup(connector);
 416 +}
 417 +
 418 +static int vc4_vec_connector_get_modes(struct drm_connector *connector)
 419 +{
 420 +       struct drm_connector_state *state = connector->state;
 421 +       struct drm_display_mode *mode;
 422 +
 423 +       mode = drm_mode_duplicate(connector->dev,
 424 +                                 vc4_vec_tv_modes[state->tv.mode].mode);
 425 +       if (!mode) {
 426 +               DRM_ERROR("Failed to create a new display mode\n");
 427 +               return -ENOMEM;
 428 +       }
 429 +
 430 +       drm_mode_probed_add(connector, mode);
 431 +
 432 +       return 1;
 433 +}
 434 +
 435 +static const struct drm_connector_funcs vc4_vec_connector_funcs = {
 436 +       .dpms = drm_atomic_helper_connector_dpms,
 437 +       .detect = vc4_vec_connector_detect,
 438 +       .fill_modes = drm_helper_probe_single_connector_modes,
 439 +       .set_property = drm_atomic_helper_connector_set_property,
 440 +       .destroy = vc4_vec_connector_destroy,
 441 +       .reset = drm_atomic_helper_connector_reset,
 442 +       .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 443 +       .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 444 +};
 445 +
 446 +static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
 447 +       .get_modes = vc4_vec_connector_get_modes,
 448 +};
 449 +
 450 +static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev,
 451 +                                                   struct vc4_vec *vec)
 452 +{
 453 +       struct drm_connector *connector = NULL;
 454 +       struct vc4_vec_connector *vec_connector;
 455 +
 456 +       vec_connector = devm_kzalloc(dev->dev, sizeof(*vec_connector),
 457 +                                    GFP_KERNEL);
 458 +       if (!vec_connector)
 459 +               return ERR_PTR(-ENOMEM);
 460 +
 461 +       connector = &vec_connector->base;
 462 +       connector->interlace_allowed = true;
 463 +
 464 +       vec_connector->encoder = vec->encoder;
 465 +       vec_connector->vec = vec;
 466 +
 467 +       drm_connector_init(dev, connector, &vc4_vec_connector_funcs,
 468 +                          DRM_MODE_CONNECTOR_Composite);
 469 +       drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
 470 +
 471 +       drm_object_attach_property(&connector->base,
 472 +                                  dev->mode_config.tv_mode_property,
 473 +                                  VC4_VEC_TV_MODE_NTSC);
 474 +       vec->tv_mode = &vc4_vec_tv_modes[VC4_VEC_TV_MODE_NTSC];
 475 +
 476 +       drm_mode_connector_attach_encoder(connector, vec->encoder);
 477 +
 478 +       return connector;
 479 +}
 480 +
 481 +static const struct drm_encoder_funcs vc4_vec_encoder_funcs = {
 482 +       .destroy = drm_encoder_cleanup,
 483 +};
 484 +
 485 +static void vc4_vec_encoder_disable(struct drm_encoder *encoder)
 486 +{
 487 +       struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
 488 +       struct vc4_vec *vec = vc4_vec_encoder->vec;
 489 +       int ret;
 490 +
 491 +       VEC_WRITE(VEC_CFG, 0);
 492 +       VEC_WRITE(VEC_DAC_MISC,
 493 +                 VEC_DAC_MISC_VCD_PWRDN |
 494 +                 VEC_DAC_MISC_BIAS_PWRDN |
 495 +                 VEC_DAC_MISC_DAC_PWRDN |
 496 +                 VEC_DAC_MISC_LDO_PWRDN);
 497 +
 498 +       clk_disable_unprepare(vec->clock);
 499 +
 500 +       ret = pm_runtime_put(&vec->pdev->dev);
 501 +       if (ret < 0) {
 502 +               DRM_ERROR("Failed to release power domain: %d\n", ret);
 503 +               return;
 504 +       }
 505 +}
 506 +
 507 +static void vc4_vec_encoder_enable(struct drm_encoder *encoder)
 508 +{
 509 +       struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
 510 +       struct vc4_vec *vec = vc4_vec_encoder->vec;
 511 +       int ret;
 512 +
 513 +       ret = pm_runtime_get_sync(&vec->pdev->dev);
 514 +       if (ret < 0) {
 515 +               DRM_ERROR("Failed to retain power domain: %d\n", ret);
 516 +               return;
 517 +       }
 518 +
 519 +       /*
 520 +        * We need to set the clock rate each time we enable the encoder
 521 +        * because there's a chance we share the same parent with the HDMI
 522 +        * clock, and both drivers are requesting different rates.
 523 +        * The good news is, these 2 encoders cannot be enabled at the same
 524 +        * time, thus preventing incompatible rate requests.
 525 +        */
 526 +       ret = clk_set_rate(vec->clock, 108000000);
 527 +       if (ret) {
 528 +               DRM_ERROR("Failed to set clock rate: %d\n", ret);
 529 +               return;
 530 +       }
 531 +
 532 +       ret = clk_prepare_enable(vec->clock);
 533 +       if (ret) {
 534 +               DRM_ERROR("Failed to turn on core clock: %d\n", ret);
 535 +               return;
 536 +       }
 537 +
 538 +       /* Reset the different blocks */
 539 +       VEC_WRITE(VEC_WSE_RESET, 1);
 540 +       VEC_WRITE(VEC_SOFT_RESET, 1);
 541 +
 542 +       /* Disable the CGSM-A and WSE blocks */
 543 +       VEC_WRITE(VEC_WSE_CONTROL, 0);
 544 +
 545 +       /* Write config common to all modes. */
 546 +
 547 +       /*
 548 +        * Color subcarrier phase: phase = 360 * SCHPH / 256.
 549 +        * 0x28 <=> 39.375 deg.
 550 +        */
 551 +       VEC_WRITE(VEC_SCHPH, 0x28);
 552 +
 553 +       /*
 554 +        * Reset to default values.
 555 +        */
 556 +       VEC_WRITE(VEC_CLMP0_START, 0xac);
 557 +       VEC_WRITE(VEC_CLMP0_END, 0xec);
 558 +       VEC_WRITE(VEC_CONFIG2,
 559 +                 VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS);
 560 +       VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
 561 +       VEC_WRITE(VEC_DAC_CONFIG,
 562 +                 VEC_DAC_CONFIG_DAC_CTRL(0xc) |
 563 +                 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
 564 +                 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46));
 565 +
 566 +       /* Mask all interrupts. */
 567 +       VEC_WRITE(VEC_MASK0, 0);
 568 +
 569 +       vec->tv_mode->mode_set(vec);
 570 +
 571 +       VEC_WRITE(VEC_DAC_MISC,
 572 +                 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
 573 +       VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
 574 +}
 575 +
 576 +
 577 +static bool vc4_vec_encoder_mode_fixup(struct drm_encoder *encoder,
 578 +                                      const struct drm_display_mode *mode,
 579 +                                      struct drm_display_mode *adjusted_mode)
 580 +{
 581 +       return true;
 582 +}
 583 +
 584 +static void vc4_vec_encoder_atomic_mode_set(struct drm_encoder *encoder,
 585 +                                       struct drm_crtc_state *crtc_state,
 586 +                                       struct drm_connector_state *conn_state)
 587 +{
 588 +       struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
 589 +       struct vc4_vec *vec = vc4_vec_encoder->vec;
 590 +
 591 +       vec->tv_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
 592 +}
 593 +
 594 +static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
 595 +                                       struct drm_crtc_state *crtc_state,
 596 +                                       struct drm_connector_state *conn_state)
 597 +{
 598 +       const struct vc4_vec_tv_mode *vec_mode;
 599 +
 600 +       vec_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
 601 +
 602 +       if (conn_state->crtc &&
 603 +           !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode))
 604 +               return -EINVAL;
 605 +
 606 +       return 0;
 607 +}
 608 +
 609 +static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
 610 +       .disable = vc4_vec_encoder_disable,
 611 +       .enable = vc4_vec_encoder_enable,
 612 +       .mode_fixup = vc4_vec_encoder_mode_fixup,
 613 +       .atomic_check = vc4_vec_encoder_atomic_check,
 614 +       .atomic_mode_set = vc4_vec_encoder_atomic_mode_set,
 615 +};
 616 +
 617 +static const struct of_device_id vc4_vec_dt_match[] = {
 618 +       { .compatible = "brcm,bcm2835-vec", .data = NULL },
 619 +       { /* sentinel */ },
 620 +};
 621 +
 622 +static const char * const tv_mode_names[] = {
 623 +       [VC4_VEC_TV_MODE_NTSC] = "NTSC",
 624 +       [VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J",
 625 +       [VC4_VEC_TV_MODE_PAL] = "PAL",
 626 +       [VC4_VEC_TV_MODE_PAL_M] = "PAL-M",
 627 +};
 628 +
 629 +static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
 630 +{
 631 +       struct platform_device *pdev = to_platform_device(dev);
 632 +       struct drm_device *drm = dev_get_drvdata(master);
 633 +       struct vc4_dev *vc4 = to_vc4_dev(drm);
 634 +       struct vc4_vec *vec;
 635 +       struct vc4_vec_encoder *vc4_vec_encoder;
 636 +       int ret;
 637 +
 638 +       ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names),
 639 +                                           tv_mode_names);
 640 +       if (ret)
 641 +               return ret;
 642 +
 643 +       vec = devm_kzalloc(dev, sizeof(*vec), GFP_KERNEL);
 644 +       if (!vec)
 645 +               return -ENOMEM;
 646 +
 647 +       vc4_vec_encoder = devm_kzalloc(dev, sizeof(*vc4_vec_encoder),
 648 +                                      GFP_KERNEL);
 649 +       if (!vc4_vec_encoder)
 650 +               return -ENOMEM;
 651 +       vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC;
 652 +       vc4_vec_encoder->vec = vec;
 653 +       vec->encoder = &vc4_vec_encoder->base.base;
 654 +
 655 +       vec->pdev = pdev;
 656 +       vec->regs = vc4_ioremap_regs(pdev, 0);
 657 +       if (IS_ERR(vec->regs))
 658 +               return PTR_ERR(vec->regs);
 659 +
 660 +       vec->clock = devm_clk_get(dev, NULL);
 661 +       if (IS_ERR(vec->clock)) {
 662 +               ret = PTR_ERR(vec->clock);
 663 +               if (ret != -EPROBE_DEFER)
 664 +                       DRM_ERROR("Failed to get clock: %d\n", ret);
 665 +               return ret;
 666 +       }
 667 +
 668 +       pm_runtime_enable(dev);
 669 +
 670 +       drm_encoder_init(drm, vec->encoder, &vc4_vec_encoder_funcs,
 671 +                        DRM_MODE_ENCODER_TVDAC, NULL);
 672 +       drm_encoder_helper_add(vec->encoder, &vc4_vec_encoder_helper_funcs);
 673 +
 674 +       vec->connector = vc4_vec_connector_init(drm, vec);
 675 +       if (IS_ERR(vec->connector)) {
 676 +               ret = PTR_ERR(vec->connector);
 677 +               goto err_destroy_encoder;
 678 +       }
 679 +
 680 +       dev_set_drvdata(dev, vec);
 681 +
 682 +       vc4->vec = vec;
 683 +
 684 +       return 0;
 685 +
 686 +err_destroy_encoder:
 687 +       drm_encoder_cleanup(vec->encoder);
 688 +       pm_runtime_disable(dev);
 689 +
 690 +       return ret;
 691 +}
 692 +
 693 +static void vc4_vec_unbind(struct device *dev, struct device *master,
 694 +                          void *data)
 695 +{
 696 +       struct drm_device *drm = dev_get_drvdata(master);
 697 +       struct vc4_dev *vc4 = to_vc4_dev(drm);
 698 +       struct vc4_vec *vec = dev_get_drvdata(dev);
 699 +
 700 +       vc4_vec_connector_destroy(vec->connector);
 701 +       drm_encoder_cleanup(vec->encoder);
 702 +       pm_runtime_disable(dev);
 703 +
 704 +       vc4->vec = NULL;
 705 +}
 706 +
 707 +static const struct component_ops vc4_vec_ops = {
 708 +       .bind   = vc4_vec_bind,
 709 +       .unbind = vc4_vec_unbind,
 710 +};
 711 +
 712 +static int vc4_vec_dev_probe(struct platform_device *pdev)
 713 +{
 714 +       return component_add(&pdev->dev, &vc4_vec_ops);
 715 +}
 716 +
 717 +static int vc4_vec_dev_remove(struct platform_device *pdev)
 718 +{
 719 +       component_del(&pdev->dev, &vc4_vec_ops);
 720 +       return 0;
 721 +}
 722 +
 723 +struct platform_driver vc4_vec_driver = {
 724 +       .probe = vc4_vec_dev_probe,
 725 +       .remove = vc4_vec_dev_remove,
 726 +       .driver = {
 727 +               .name = "vc4_vec",
 728 +               .of_match_table = vc4_vec_dt_match,
 729 +       },
 730 +};