target/linux/brcm2708/patches-4.4/0265-clk-bcm2835-add-missing-PLL-clock-dividers.patch

   1 From 4f420c264a38a1eaec12a52f99f3b315133bca69 Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Mon, 29 Feb 2016 15:43:56 +0000
   4 Subject: [PATCH 265/304] clk: bcm2835: add missing PLL clock dividers
   5
   6 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
   7 Signed-off-by: Eric Anholt <eric@anholt.net>
   8 Reviewed-by: Eric Anholt <eric@anholt.net>
   9 (cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32)
  10 ---
  11  drivers/clk/bcm/clk-bcm2835.c       | 32 ++++++++++++++++++++++++++++++++
  12  include/dt-bindings/clock/bcm2835.h |  5 +++++
  13  2 files changed, 37 insertions(+)
  14
  15 --- a/drivers/clk/bcm/clk-bcm2835.c
  16 +++ b/drivers/clk/bcm/clk-bcm2835.c
  17 @@ -1383,6 +1383,22 @@ static const struct bcm2835_clk_desc clk
  18                 .load_mask = CM_PLLA_LOADPER,
  19                 .hold_mask = CM_PLLA_HOLDPER,
  20                 .fixed_divider = 1),
  21 +       [BCM2835_PLLA_DSI0]     = REGISTER_PLL_DIV(
  22 +               .name = "plla_dsi0",
  23 +               .source_pll = "plla",
  24 +               .cm_reg = CM_PLLA,
  25 +               .a2w_reg = A2W_PLLA_DSI0,
  26 +               .load_mask = CM_PLLA_LOADDSI0,
  27 +               .hold_mask = CM_PLLA_HOLDDSI0,
  28 +               .fixed_divider = 1),
  29 +       [BCM2835_PLLA_CCP2]     = REGISTER_PLL_DIV(
  30 +               .name = "plla_ccp2",
  31 +               .source_pll = "plla",
  32 +               .cm_reg = CM_PLLA,
  33 +               .a2w_reg = A2W_PLLA_CCP2,
  34 +               .load_mask = CM_PLLA_LOADCCP2,
  35 +               .hold_mask = CM_PLLA_HOLDCCP2,
  36 +               .fixed_divider = 1),
  37
  38         /* PLLB is used for the ARM's clock. */
  39         [BCM2835_PLLB]          = REGISTER_PLL(
  40 @@ -1497,6 +1513,22 @@ static const struct bcm2835_clk_desc clk
  41                 .load_mask = CM_PLLD_LOADPER,
  42                 .hold_mask = CM_PLLD_HOLDPER,
  43                 .fixed_divider = 1),
  44 +       [BCM2835_PLLD_DSI0]     = REGISTER_PLL_DIV(
  45 +               .name = "plld_dsi0",
  46 +               .source_pll = "plld",
  47 +               .cm_reg = CM_PLLD,
  48 +               .a2w_reg = A2W_PLLD_DSI0,
  49 +               .load_mask = CM_PLLD_LOADDSI0,
  50 +               .hold_mask = CM_PLLD_HOLDDSI0,
  51 +               .fixed_divider = 1),
  52 +       [BCM2835_PLLD_DSI1]     = REGISTER_PLL_DIV(
  53 +               .name = "plld_dsi1",
  54 +               .source_pll = "plld",
  55 +               .cm_reg = CM_PLLD,
  56 +               .a2w_reg = A2W_PLLD_DSI1,
  57 +               .load_mask = CM_PLLD_LOADDSI1,
  58 +               .hold_mask = CM_PLLD_HOLDDSI1,
  59 +               .fixed_divider = 1),
  60
  61         /*
  62          * PLLH is used to supply the pixel clock or the AUX clock for the
  63 --- a/include/dt-bindings/clock/bcm2835.h
  64 +++ b/include/dt-bindings/clock/bcm2835.h
  65 @@ -45,3 +45,8 @@
  66  #define BCM2835_CLOCK_PERI_IMAGE       29
  67  #define BCM2835_CLOCK_PWM              30
  68  #define BCM2835_CLOCK_PCM              31
  69 +
  70 +#define BCM2835_PLLA_DSI0              32
  71 +#define BCM2835_PLLA_CCP2              33
  72 +#define BCM2835_PLLD_DSI0              34
  73 +#define BCM2835_PLLD_DSI1              35