target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch

   1 From 3f26e43abb4c245d41dfbed03d82c3bc36044b04 Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Mon, 29 Feb 2016 15:43:57 +0000
   4 Subject: [PATCH] clk: bcm2835: add missing osc and per clocks
   5
   6 Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E,
   7 and DSI1E.  PULSE is not added because it has an extra divider.
   8
   9 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  10 Signed-off-by: Eric Anholt <eric@anholt.net>
  11 Reviewed-by: Eric Anholt <eric@anholt.net>
  12 (cherry picked from commit d3d6f15fd376e3dbba851724057b112558c70b79)
  13 ---
  14  drivers/clk/bcm/clk-bcm2835.c       | 90 +++++++++++++++++++++++++++++++++++++
  15  include/dt-bindings/clock/bcm2835.h | 14 ++++++
  16  2 files changed, 104 insertions(+)
  17
  18 --- a/drivers/clk/bcm/clk-bcm2835.c
  19 +++ b/drivers/clk/bcm/clk-bcm2835.c
  20 @@ -117,6 +117,8 @@
  21  #define CM_SDCCTL              0x1a8
  22  #define CM_SDCDIV              0x1ac
  23  #define CM_ARMCTL              0x1b0
  24 +#define CM_AVEOCTL             0x1b8
  25 +#define CM_AVEODIV             0x1bc
  26  #define CM_EMMCCTL             0x1c0
  27  #define CM_EMMCDIV             0x1c4
  28
  29 @@ -1610,6 +1612,12 @@ static const struct bcm2835_clk_desc clk
  30                 .div_reg = CM_TSENSDIV,
  31                 .int_bits = 5,
  32                 .frac_bits = 0),
  33 +       [BCM2835_CLOCK_TEC]     = REGISTER_OSC_CLK(
  34 +               .name = "tec",
  35 +               .ctl_reg = CM_TECCTL,
  36 +               .div_reg = CM_TECDIV,
  37 +               .int_bits = 6,
  38 +               .frac_bits = 0),
  39
  40         /* clocks with vpu parent mux */
  41         [BCM2835_CLOCK_H264]    = REGISTER_VPU_CLK(
  42 @@ -1624,6 +1632,7 @@ static const struct bcm2835_clk_desc clk
  43                 .div_reg = CM_ISPDIV,
  44                 .int_bits = 4,
  45                 .frac_bits = 8),
  46 +
  47         /*
  48          * Secondary SDRAM clock.  Used for low-voltage modes when the PLL
  49          * in the SDRAM controller can't be used.
  50 @@ -1655,6 +1664,36 @@ static const struct bcm2835_clk_desc clk
  51                 .is_vpu_clock = true),
  52
  53         /* clocks with per parent mux */
  54 +       [BCM2835_CLOCK_AVEO]    = REGISTER_PER_CLK(
  55 +               .name = "aveo",
  56 +               .ctl_reg = CM_AVEOCTL,
  57 +               .div_reg = CM_AVEODIV,
  58 +               .int_bits = 4,
  59 +               .frac_bits = 0),
  60 +       [BCM2835_CLOCK_CAM0]    = REGISTER_PER_CLK(
  61 +               .name = "cam0",
  62 +               .ctl_reg = CM_CAM0CTL,
  63 +               .div_reg = CM_CAM0DIV,
  64 +               .int_bits = 4,
  65 +               .frac_bits = 8),
  66 +       [BCM2835_CLOCK_CAM1]    = REGISTER_PER_CLK(
  67 +               .name = "cam1",
  68 +               .ctl_reg = CM_CAM1CTL,
  69 +               .div_reg = CM_CAM1DIV,
  70 +               .int_bits = 4,
  71 +               .frac_bits = 8),
  72 +       [BCM2835_CLOCK_DFT]     = REGISTER_PER_CLK(
  73 +               .name = "dft",
  74 +               .ctl_reg = CM_DFTCTL,
  75 +               .div_reg = CM_DFTDIV,
  76 +               .int_bits = 5,
  77 +               .frac_bits = 0),
  78 +       [BCM2835_CLOCK_DPI]     = REGISTER_PER_CLK(
  79 +               .name = "dpi",
  80 +               .ctl_reg = CM_DPICTL,
  81 +               .div_reg = CM_DPIDIV,
  82 +               .int_bits = 4,
  83 +               .frac_bits = 8),
  84
  85         /* Arasan EMMC clock */
  86         [BCM2835_CLOCK_EMMC]    = REGISTER_PER_CLK(
  87 @@ -1663,6 +1702,29 @@ static const struct bcm2835_clk_desc clk
  88                 .div_reg = CM_EMMCDIV,
  89                 .int_bits = 4,
  90                 .frac_bits = 8),
  91 +
  92 +       /* General purpose (GPIO) clocks */
  93 +       [BCM2835_CLOCK_GP0]     = REGISTER_PER_CLK(
  94 +               .name = "gp0",
  95 +               .ctl_reg = CM_GP0CTL,
  96 +               .div_reg = CM_GP0DIV,
  97 +               .int_bits = 12,
  98 +               .frac_bits = 12,
  99 +               .is_mash_clock = true),
 100 +       [BCM2835_CLOCK_GP1]     = REGISTER_PER_CLK(
 101 +               .name = "gp1",
 102 +               .ctl_reg = CM_GP1CTL,
 103 +               .div_reg = CM_GP1DIV,
 104 +               .int_bits = 12,
 105 +               .frac_bits = 12,
 106 +               .is_mash_clock = true),
 107 +       [BCM2835_CLOCK_GP2]     = REGISTER_PER_CLK(
 108 +               .name = "gp2",
 109 +               .ctl_reg = CM_GP2CTL,
 110 +               .div_reg = CM_GP2DIV,
 111 +               .int_bits = 12,
 112 +               .frac_bits = 12),
 113 +
 114         /* HDMI state machine */
 115         [BCM2835_CLOCK_HSM]     = REGISTER_PER_CLK(
 116                 .name = "hsm",
 117 @@ -1684,12 +1746,26 @@ static const struct bcm2835_clk_desc clk
 118                 .int_bits = 12,
 119                 .frac_bits = 12,
 120                 .is_mash_clock = true),
 121 +       [BCM2835_CLOCK_SLIM]    = REGISTER_PER_CLK(
 122 +               .name = "slim",
 123 +               .ctl_reg = CM_SLIMCTL,
 124 +               .div_reg = CM_SLIMDIV,
 125 +               .int_bits = 12,
 126 +               .frac_bits = 12,
 127 +               .is_mash_clock = true),
 128 +       [BCM2835_CLOCK_SMI]     = REGISTER_PER_CLK(
 129 +               .name = "smi",
 130 +               .ctl_reg = CM_SMICTL,
 131 +               .div_reg = CM_SMIDIV,
 132 +               .int_bits = 4,
 133 +               .frac_bits = 8),
 134         [BCM2835_CLOCK_UART]    = REGISTER_PER_CLK(
 135                 .name = "uart",
 136                 .ctl_reg = CM_UARTCTL,
 137                 .div_reg = CM_UARTDIV,
 138                 .int_bits = 10,
 139                 .frac_bits = 12),
 140 +
 141         /* TV encoder clock.  Only operating frequency is 108Mhz.  */
 142         [BCM2835_CLOCK_VEC]     = REGISTER_PER_CLK(
 143                 .name = "vec",
 144 @@ -1698,6 +1774,20 @@ static const struct bcm2835_clk_desc clk
 145                 .int_bits = 4,
 146                 .frac_bits = 0),
 147
 148 +       /* dsi clocks */
 149 +       [BCM2835_CLOCK_DSI0E]   = REGISTER_PER_CLK(
 150 +               .name = "dsi0e",
 151 +               .ctl_reg = CM_DSI0ECTL,
 152 +               .div_reg = CM_DSI0EDIV,
 153 +               .int_bits = 4,
 154 +               .frac_bits = 8),
 155 +       [BCM2835_CLOCK_DSI1E]   = REGISTER_PER_CLK(
 156 +               .name = "dsi1e",
 157 +               .ctl_reg = CM_DSI1ECTL,
 158 +               .div_reg = CM_DSI1EDIV,
 159 +               .int_bits = 4,
 160 +               .frac_bits = 8),
 161 +
 162         /* the gates */
 163
 164         /*
 165 --- a/include/dt-bindings/clock/bcm2835.h
 166 +++ b/include/dt-bindings/clock/bcm2835.h
 167 @@ -50,3 +50,17 @@
 168  #define BCM2835_PLLA_CCP2              33
 169  #define BCM2835_PLLD_DSI0              34
 170  #define BCM2835_PLLD_DSI1              35
 171 +
 172 +#define BCM2835_CLOCK_AVEO             36
 173 +#define BCM2835_CLOCK_DFT              37
 174 +#define BCM2835_CLOCK_GP0              38
 175 +#define BCM2835_CLOCK_GP1              39
 176 +#define BCM2835_CLOCK_GP2              40
 177 +#define BCM2835_CLOCK_SLIM             41
 178 +#define BCM2835_CLOCK_SMI              42
 179 +#define BCM2835_CLOCK_TEC              43
 180 +#define BCM2835_CLOCK_DPI              44
 181 +#define BCM2835_CLOCK_CAM0             45
 182 +#define BCM2835_CLOCK_CAM1             46
 183 +#define BCM2835_CLOCK_DSI0E            47
 184 +#define BCM2835_CLOCK_DSI1E            48