target/linux/brcm2708/patches-4.4/0196-drm-vc4-Fix-the-clear-color-for-the-first-tile-rende.patch

   1 From 7ff02c91259682b40b5ce8a90f114925d71572c0 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Mon, 25 Jan 2016 13:52:41 -0800
   4 Subject: [PATCH 196/232] drm/vc4: Fix the clear color for the first tile
   5  rendered.
   6
   7 Apparently in hardware (as opposed to simulation), the clear colors
   8 need to be uploaded before the render config, otherwise they won't
   9 take effect.  Fixes igt's vc4_wait_bo/used-bo-* subtests.
  10
  11 Signed-off-by: Eric Anholt <eric@anholt.net>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_render_cl.c | 18 +++++++++---------
  14  1 file changed, 9 insertions(+), 9 deletions(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_render_cl.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
  18 @@ -321,15 +321,6 @@ static int vc4_create_rcl_bo(struct drm_
  19         list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head,
  20                       &exec->unref_list);
  21
  22 -       rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
  23 -       rcl_u32(setup,
  24 -               (setup->color_write ? (setup->color_write->paddr +
  25 -                                      args->color_write.offset) :
  26 -                0));
  27 -       rcl_u16(setup, args->width);
  28 -       rcl_u16(setup, args->height);
  29 -       rcl_u16(setup, args->color_write.bits);
  30 -
  31         /* The tile buffer gets cleared when the previous tile is stored.  If
  32          * the clear values changed between frames, then the tile buffer has
  33          * stale clear values in it, so we have to do a store in None mode (no
  34 @@ -349,6 +340,15 @@ static int vc4_create_rcl_bo(struct drm_
  35                 rcl_u32(setup, 0); /* no address, since we're in None mode */
  36         }
  37
  38 +       rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
  39 +       rcl_u32(setup,
  40 +               (setup->color_write ? (setup->color_write->paddr +
  41 +                                      args->color_write.offset) :
  42 +                0));
  43 +       rcl_u16(setup, args->width);
  44 +       rcl_u16(setup, args->height);
  45 +       rcl_u16(setup, args->color_write.bits);
  46 +
  47         for (y = min_y_tile; y <= max_y_tile; y++) {
  48                 for (x = min_x_tile; x <= max_x_tile; x++) {
  49                         bool first = (x == min_x_tile && y == min_y_tile);