2 * Low-Level PCI and SB support for BCM47xx (Linux support code)
4 * Copyright 2006, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14 #include <linux/config.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
23 #include <asm/paccess.h>
34 /* Global SB handle */
35 extern sb_t *bcm947xx_sbh;
36 extern spinlock_t bcm947xx_sbh_lock;
39 #define sbh bcm947xx_sbh
40 #define sbh_lock bcm947xx_sbh_lock
43 sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
48 spin_lock_irqsave(&sbh_lock, flags);
49 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
50 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
51 spin_unlock_irqrestore(&sbh_lock, flags);
52 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
56 sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
61 spin_lock_irqsave(&sbh_lock, flags);
62 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
63 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
64 spin_unlock_irqrestore(&sbh_lock, flags);
65 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
69 sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
74 spin_lock_irqsave(&sbh_lock, flags);
75 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
76 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
77 spin_unlock_irqrestore(&sbh_lock, flags);
78 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
82 sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
87 spin_lock_irqsave(&sbh_lock, flags);
88 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
89 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
90 spin_unlock_irqrestore(&sbh_lock, flags);
91 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
95 sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
100 spin_lock_irqsave(&sbh_lock, flags);
101 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
102 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
103 spin_unlock_irqrestore(&sbh_lock, flags);
104 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
108 sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
113 spin_lock_irqsave(&sbh_lock, flags);
114 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
115 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
116 spin_unlock_irqrestore(&sbh_lock, flags);
117 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
120 static struct pci_ops pcibios_ops = {
121 sbpci_read_config_byte,
122 sbpci_read_config_word,
123 sbpci_read_config_dword,
124 sbpci_write_config_byte,
125 sbpci_write_config_word,
126 sbpci_write_config_dword
135 if (!(sbh = sb_kattach(SB_OSH)))
136 panic("sb_kattach failed");
137 spin_lock_init(&sbh_lock);
139 spin_lock_irqsave(&sbh_lock, flags);
141 spin_unlock_irqrestore(&sbh_lock, flags);
143 set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
144 mdelay(300); /* workaround for atheros cards */
146 /* Scan the SB bus */
147 pci_scan_bus(0, &pcibios_ops, NULL);
152 pcibios_setup(char *str)
154 if (!strncmp(str, "ban=", 4)) {
155 sbpci_ban(simple_strtoul(str + 4, NULL, 0));
162 static u32 pci_iobase = 0x100;
163 static u32 pci_membase = SB_PCI_DMA;
164 static u32 pcmcia_membase = 0x40004000;
167 pcibios_fixup_bus(struct pci_bus *b)
169 struct list_head *ln;
171 struct resource *res;
176 printk("PCI: Fixing up bus %d\n", b->number);
179 if (b->number == 0) {
180 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
182 /* Fix up interrupt lines */
183 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
185 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
189 /* Fix up external PCI */
191 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
193 /* Fix up resource bases */
194 for (pos = 0; pos < 6; pos++) {
195 res = &d->resource[pos];
196 base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
198 size = res->end - res->start + 1;
199 if (*base & (size - 1))
200 *base = (*base + size) & ~(size - 1);
202 res->end = res->start + size - 1;
204 pci_write_config_dword(d,
205 PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
207 /* Fix up PCI bridge BAR0 only */
208 if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
211 /* Fix up interrupt lines */
212 if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
213 d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
214 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
220 pcibios_assign_all_busses(void)
226 pcibios_align_resource(void *data, struct resource *res,
227 unsigned long size, unsigned long align)
232 pcibios_enable_resources(struct pci_dev *dev)
238 /* External PCI only */
239 if (dev->bus->number == 0)
242 pci_read_config_word(dev, PCI_COMMAND, &cmd);
244 for (idx = 0; idx < 6; idx++) {
245 r = &dev->resource[idx];
246 if (r->flags & IORESOURCE_IO)
247 cmd |= PCI_COMMAND_IO;
248 if (r->flags & IORESOURCE_MEM)
249 cmd |= PCI_COMMAND_MEMORY;
251 if (dev->resource[PCI_ROM_RESOURCE].start)
252 cmd |= PCI_COMMAND_MEMORY;
253 if (cmd != old_cmd) {
254 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
255 pci_write_config_word(dev, PCI_COMMAND, cmd);
261 pcibios_enable_device(struct pci_dev *dev, int mask)
267 /* External PCI device enable */
268 if (dev->bus->number != 0)
269 return pcibios_enable_resources(dev);
271 /* These cores come out of reset enabled */
272 if (dev->device == SB_MIPS ||
273 dev->device == SB_MIPS33 ||
274 dev->device == SB_EXTIF ||
275 dev->device == SB_CC)
278 spin_lock_irqsave(&sbh_lock, flags);
279 coreidx = sb_coreidx(sbh);
280 regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
282 return PCIBIOS_DEVICE_NOT_FOUND;
285 * The USB core requires a special bit to be set during core
286 * reset to enable host (OHCI) mode. Resetting the SB core in
287 * pcibios_enable_device() is a hack for compatibility with
288 * vanilla usb-ohci so that it does not have to know about
289 * SB. A driver that wants to use the USB core in device mode
290 * should know about SB and should reset the bit back to 0
291 * after calling pcibios_enable_device().
293 if (sb_coreid(sbh) == SB_USB) {
294 printk(KERN_INFO "SB USB 1.1 init\n");
295 sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
296 sb_core_reset(sbh, 1 << 29, 0);
299 * USB 2.0 special considerations:
301 * 1. Since the core supports both OHCI and EHCI functions, it must
302 * only be reset once.
304 * 2. In addition to the standard SB reset sequence, the Host Control
305 * Register must be programmed to bring the USB core and various
306 * phy components out of reset.
308 else if (sb_coreid(sbh) == SB_USB20H) {
310 uint corerev = sb_corerev(sbh);
312 printk(KERN_INFO "SB USB20H init\n");
313 printk(KERN_INFO "SB COREREV: %d\n", corerev);
315 if (!sb_iscoreup(sbh)) {
317 printk(KERN_INFO "SB USB20H resetting\n");
319 sb_core_reset(sbh, 0, 0);
320 writel(0x7FF, (ulong)regs + 0x200);
323 /* PRxxxx: War for 5354 failures. */
324 if (corerev == 1 || corerev == 2) {
327 /* Change Flush control reg */
328 tmp = readl((uintptr)regs + 0x400);
330 writel(tmp, (uintptr)regs + 0x400);
331 tmp = readl((uintptr)regs + 0x400);
332 printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
334 /* Change Shim control reg */
335 tmp = readl((uintptr)regs + 0x304);
337 writel(tmp, (uintptr)regs + 0x304);
338 tmp = readl((uintptr)regs + 0x304);
339 printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
343 sb_core_reset(sbh, 0, 0);
345 sb_setcoreidx(sbh, coreidx);
346 spin_unlock_irqrestore(&sbh_lock, flags);
352 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
353 struct resource *res, int resource)
355 unsigned long where, size;
358 /* External PCI only */
359 if (dev->bus->number == 0)
362 where = PCI_BASE_ADDRESS_0 + (resource * 4);
363 size = res->end - res->start;
364 pci_read_config_dword(dev, where, ®);
366 if (dev->bus->number == 1)
367 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
371 pci_write_config_dword(dev, where, reg);
375 quirk_sbpci_bridge(struct pci_dev *dev)
377 if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
380 printk("PCI: Fixing up bridge\n");
382 /* Enable PCI bridge bus mastering and memory space */
384 pcibios_enable_resources(dev);
386 /* Enable PCI bridge BAR1 prefetch and burst */
387 pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
390 struct pci_fixup pcibios_fixups[] = {
391 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
396 * If we set up a device for bus mastering, we need to check the latency
397 * timer as certain crappy BIOSes forget to set it properly.
399 unsigned int pcibios_max_latency = 255;
401 void pcibios_set_master(struct pci_dev *dev)
404 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
406 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
407 else if (lat > pcibios_max_latency)
408 lat = pcibios_max_latency;
411 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
412 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);