target/linux/bcm27xx/patches-5.4/950-0571-drm-vc4-crtc-Add-BCM2711-pixelvalves.patch

   1 From aa43601d97bf9136b657259f44c03a6a30b70d07 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 26 Dec 2019 11:35:58 +0100
   4 Subject: [PATCH] drm/vc4: crtc: Add BCM2711 pixelvalves
   5
   6 The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add
   7 support for them.
   8
   9 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  10 ---
  11  drivers/gpu/drm/vc4/vc4_crtc.c | 82 +++++++++++++++++++++++++++++++++-
  12  drivers/gpu/drm/vc4/vc4_regs.h |  6 +++
  13  2 files changed, 86 insertions(+), 2 deletions(-)
  14
  15 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  16 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  17 @@ -273,6 +273,13 @@ static u32 vc4_get_fifo_full_level(struc
  18         case PV_CONTROL_FORMAT_24:
  19         case PV_CONTROL_FORMAT_DSIV_24:
  20         default:
  21 +               /*
  22 +                * For some reason, the pixelvalve4 doesn't work with
  23 +                * the usual formula and will only work with 32.
  24 +                */
  25 +               if (vc4_crtc->data->hvs_output == 5)
  26 +                       return 32;
  27 +
  28                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
  29         }
  30  }
  31 @@ -281,8 +288,14 @@ static u32 vc4_crtc_get_fifo_full_level_
  32                                              u32 format)
  33  {
  34         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
  35 -       return VC4_SET_FIELD(level & 0x3f,
  36 -                            PV_CONTROL_FIFO_LEVEL);
  37 +       u32 ret = 0;
  38 +
  39 +       if (level > 0x3f)
  40 +               ret |= VC4_SET_FIELD((level >> 6) & 0x3,
  41 +                                    PV5_CONTROL_FIFO_LEVEL_HIGH);
  42 +
  43 +       return ret | VC4_SET_FIELD(level & 0x3f,
  44 +                                  PV_CONTROL_FIFO_LEVEL);
  45  }
  46
  47  /*
  48 @@ -328,6 +341,9 @@ static void vc4_crtc_config_pv(struct dr
  49         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
  50         CRTC_WRITE(PV_CONTROL, 0);
  51
  52 +       CRTC_WRITE(PV_MUX_CFG,
  53 +                  VC4_SET_FIELD(8, PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
  54 +
  55         CRTC_WRITE(PV_HORZA,
  56                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
  57                                  PV_HORZA_HBP) |
  58 @@ -1115,10 +1131,72 @@ static const struct vc4_crtc_data bcm283
  59         },
  60  };
  61
  62 +static const struct vc4_crtc_data bcm2711_pv0_data = {
  63 +       .debugfs_name = "crtc0_regs",
  64 +       .hvs_available_channels = BIT(0),
  65 +       .hvs_output = 0,
  66 +       .fifo_depth = 64,
  67 +       .pixels_per_clock = 1,
  68 +       .encoder_types = {
  69 +               [0] = VC4_ENCODER_TYPE_DSI0,
  70 +               [1] = VC4_ENCODER_TYPE_DPI,
  71 +       },
  72 +};
  73 +
  74 +static const struct vc4_crtc_data bcm2711_pv1_data = {
  75 +       .debugfs_name = "crtc1_regs",
  76 +       .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
  77 +       .hvs_output = 3,
  78 +       .fifo_depth = 64,
  79 +       .pixels_per_clock = 1,
  80 +       .encoder_types = {
  81 +               [0] = VC4_ENCODER_TYPE_DSI1,
  82 +               [1] = VC4_ENCODER_TYPE_SMI,
  83 +       },
  84 +};
  85 +
  86 +static const struct vc4_crtc_data bcm2711_pv2_data = {
  87 +       .debugfs_name = "crtc2_regs",
  88 +       .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
  89 +       .hvs_output = 4,
  90 +       .fifo_depth = 256,
  91 +       .pixels_per_clock = 2,
  92 +       .encoder_types = {
  93 +               [0] = VC4_ENCODER_TYPE_HDMI0,
  94 +       },
  95 +};
  96 +
  97 +static const struct vc4_crtc_data bcm2711_pv3_data = {
  98 +       .debugfs_name = "crtc3_regs",
  99 +       .hvs_available_channels = BIT(1),
 100 +       .hvs_output = 1,
 101 +       .fifo_depth = 64,
 102 +       .pixels_per_clock = 1,
 103 +       .encoder_types = {
 104 +               [0] = VC4_ENCODER_TYPE_VEC,
 105 +       },
 106 +};
 107 +
 108 +static const struct vc4_crtc_data bcm2711_pv4_data = {
 109 +       .debugfs_name = "crtc4_regs",
 110 +       .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
 111 +       .hvs_output = 5,
 112 +       .fifo_depth = 64,
 113 +       .pixels_per_clock = 2,
 114 +       .encoder_types = {
 115 +               [0] = VC4_ENCODER_TYPE_HDMI1,
 116 +       },
 117 +};
 118 +
 119  static const struct of_device_id vc4_crtc_dt_match[] = {
 120         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
 121         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
 122         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
 123 +       { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
 124 +       { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
 125 +       { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
 126 +       { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
 127 +       { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
 128         {}
 129  };
 130
 131 --- a/drivers/gpu/drm/vc4/vc4_regs.h
 132 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
 133 @@ -130,6 +130,8 @@
 134  #define V3D_ERRSTAT  0x00f20
 135
 136  #define PV_CONTROL                             0x00
 137 +# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK      VC4_MASK(26, 25)
 138 +# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT     25
 139  # define PV_CONTROL_FORMAT_MASK                        VC4_MASK(23, 21)
 140  # define PV_CONTROL_FORMAT_SHIFT               21
 141  # define PV_CONTROL_FORMAT_24                  0
 142 @@ -209,6 +211,10 @@
 143
 144  #define PV_HACT_ACT                            0x30
 145
 146 +#define PV_MUX_CFG                             0x34
 147 +# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK    VC4_MASK(5, 2)
 148 +# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT   2
 149 +
 150  #define SCALER_CHANNELS_COUNT                  3
 151
 152  #define SCALER_DISPCTRL                         0x00000000