target/linux/bcm27xx/patches-5.4/950-0048-Add-SMI-driver.patch

   1 From c8a43c83e4cc9c18382693fc722c06a6fb97d673 Mon Sep 17 00:00:00 2001
   2 From: Luke Wren <wren6991@gmail.com>
   3 Date: Sat, 5 Sep 2015 01:14:45 +0100
   4 Subject: [PATCH] Add SMI driver
   5
   6 Signed-off-by: Luke Wren <wren6991@gmail.com>
   7
   8 MISC: bcm2835: smi: use clock manager and fix reload issues
   9
  10 Use clock manager instead of self-made clockmanager.
  11
  12 Also fix some error paths that showd up during development
  13 (especially missing release of dma resources on rmmod)
  14
  15 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  16
  17 bcm2835_smi: re-add dereference to fix DMA transfers
  18 ---
  19  .../bindings/misc/brcm,bcm2835-smi-dev.txt    |  17 +
  20  .../bindings/misc/brcm,bcm2835-smi.txt        |  48 +
  21  drivers/char/broadcom/Kconfig                 |   8 +
  22  drivers/char/broadcom/Makefile                |   2 +-
  23  drivers/char/broadcom/bcm2835_smi_dev.c       | 402 ++++++++
  24  drivers/misc/Kconfig                          |   8 +
  25  drivers/misc/Makefile                         |   1 +
  26  drivers/misc/bcm2835_smi.c                    | 955 ++++++++++++++++++
  27  include/linux/broadcom/bcm2835_smi.h          | 391 +++++++
  28  9 files changed, 1831 insertions(+), 1 deletion(-)
  29  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  30  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  31  create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c
  32  create mode 100644 drivers/misc/bcm2835_smi.c
  33  create mode 100644 include/linux/broadcom/bcm2835_smi.h
  34
  35 --- /dev/null
  36 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  37 @@ -0,0 +1,17 @@
  38 +* Broadcom BCM2835 SMI character device driver.
  39 +
  40 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  41 +SOCs, and is helpful for talking to things like parallel-interface displays
  42 +and NAND flashes (in fact, most things with a parallel register interface).
  43 +
  44 +This driver adds a character device which provides a user-space interface to
  45 +an instance of the SMI driver.
  46 +
  47 +Required properties:
  48 +- compatible: "brcm,bcm2835-smi-dev"
  49 +- smi_handle: a phandle to the smi node.
  50 +
  51 +Optional properties:
  52 +- None.
  53 +
  54 +
  55 --- /dev/null
  56 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  57 @@ -0,0 +1,48 @@
  58 +* Broadcom BCM2835 SMI driver.
  59 +
  60 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  61 +SOCs, and is helpful for talking to things like parallel-interface displays
  62 +and NAND flashes (in fact, most things with a parallel register interface).
  63 +
  64 +Required properties:
  65 +- compatible: "brcm,bcm2835-smi"
  66 +- reg: Should contain location and length of SMI registers and SMI clkman regs
  67 +- interrupts: *the* SMI interrupt.
  68 +- pinctrl-names: should be "default".
  69 +- pinctrl-0: the phandle of the gpio pin node.
  70 +- brcm,smi-clock-source: the clock source for clkman
  71 +- brcm,smi-clock-divisor: the integer clock divisor for clkman
  72 +- dmas: the dma controller phandle and the DREQ number (4 on a 2835)
  73 +- dma-names: the name used by the driver to request its channel.
  74 +  Should be "rx-tx".
  75 +
  76 +Optional properties:
  77 +- None.
  78 +
  79 +Examples:
  80 +
  81 +8 data pin configuration:
  82 +
  83 +smi: smi@7e600000 {
  84 +       compatible = "brcm,bcm2835-smi";
  85 +       reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;
  86 +       interrupts = <2 16>;
  87 +       pinctrl-names = "default";
  88 +       pinctrl-0 = <&smi_pins>;
  89 +       brcm,smi-clock-source = <6>;
  90 +       brcm,smi-clock-divisor = <4>;
  91 +       dmas = <&dma 4>;
  92 +       dma-names = "rx-tx";
  93 +
  94 +       status = "okay";
  95 +};
  96 +
  97 +smi_pins: smi_pins {
  98 +       brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  99 +       /* Alt 1: SMI */
 100 +       brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>;
 101 +       /* /CS, /WE and /OE are pulled high, as they are
 102 +          generally active low signals */
 103 +       brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>;
 104 +};
 105 +
 106 --- a/drivers/char/broadcom/Kconfig
 107 +++ b/drivers/char/broadcom/Kconfig
 108 @@ -35,3 +35,11 @@ config BCM2835_DEVGPIOMEM
 109                 on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO
 110                 register page to the user's pointer.
 111
 112 +config BCM2835_SMI_DEV
 113 +       tristate "Character device driver for BCM2835 Secondary Memory Interface"
 114 +       depends on BCM2835_SMI
 115 +       default m
 116 +       help
 117 +               This driver provides a character device interface (ioctl + read/write) to
 118 +               Broadcom's Secondary Memory interface. The low-level functionality is provided
 119 +               by the SMI driver itself.
 120 --- a/drivers/char/broadcom/Makefile
 121 +++ b/drivers/char/broadcom/Makefile
 122 @@ -2,4 +2,4 @@ obj-$(CONFIG_BCM2708_VCMEM)     += vc_mem.o
 123  obj-$(CONFIG_BCM_VC_SM)         += vc_sm/
 124
 125  obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
 126 -
 127 +obj-$(CONFIG_BCM2835_SMI_DEV)  += bcm2835_smi_dev.o
 128 --- /dev/null
 129 +++ b/drivers/char/broadcom/bcm2835_smi_dev.c
 130 @@ -0,0 +1,402 @@
 131 +/**
 132 + * Character device driver for Broadcom Secondary Memory Interface
 133 + *
 134 + * Written by Luke Wren <luke@raspberrypi.org>
 135 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 136 + *
 137 + * Redistribution and use in source and binary forms, with or without
 138 + * modification, are permitted provided that the following conditions
 139 + * are met:
 140 + * 1. Redistributions of source code must retain the above copyright
 141 + *    notice, this list of conditions, and the following disclaimer,
 142 + *    without modification.
 143 + * 2. Redistributions in binary form must reproduce the above copyright
 144 + *    notice, this list of conditions and the following disclaimer in the
 145 + *    documentation and/or other materials provided with the distribution.
 146 + * 3. The names of the above-listed copyright holders may not be used
 147 + *    to endorse or promote products derived from this software without
 148 + *    specific prior written permission.
 149 + *
 150 + * ALTERNATIVELY, this software may be distributed under the terms of the
 151 + * GNU General Public License ("GPL") version 2, as published by the Free
 152 + * Software Foundation.
 153 + *
 154 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 155 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 156 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 157 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 158 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 159 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 160 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 161 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 162 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 163 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 164 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 165 + */
 166 +
 167 +#include <linux/kernel.h>
 168 +#include <linux/module.h>
 169 +#include <linux/of.h>
 170 +#include <linux/platform_device.h>
 171 +#include <linux/slab.h>
 172 +#include <linux/mm.h>
 173 +#include <linux/pagemap.h>
 174 +#include <linux/fs.h>
 175 +#include <linux/cdev.h>
 176 +#include <linux/fs.h>
 177 +
 178 +#include <linux/broadcom/bcm2835_smi.h>
 179 +
 180 +#define DEVICE_NAME "bcm2835-smi-dev"
 181 +#define DRIVER_NAME "smi-dev-bcm2835"
 182 +#define DEVICE_MINOR 0
 183 +
 184 +static struct cdev bcm2835_smi_cdev;
 185 +static dev_t bcm2835_smi_devid;
 186 +static struct class *bcm2835_smi_class;
 187 +static struct device *bcm2835_smi_dev;
 188 +
 189 +struct bcm2835_smi_dev_instance {
 190 +       struct device *dev;
 191 +};
 192 +
 193 +static struct bcm2835_smi_instance *smi_inst;
 194 +static struct bcm2835_smi_dev_instance *inst;
 195 +
 196 +static const char *const ioctl_names[] = {
 197 +       "READ_SETTINGS",
 198 +       "WRITE_SETTINGS",
 199 +       "ADDRESS"
 200 +};
 201 +
 202 +/****************************************************************************
 203 +*
 204 +*   SMI chardev file ops
 205 +*
 206 +***************************************************************************/
 207 +static long
 208 +bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 209 +{
 210 +       long ret = 0;
 211 +
 212 +       dev_info(inst->dev, "serving ioctl...");
 213 +
 214 +       switch (cmd) {
 215 +       case BCM2835_SMI_IOC_GET_SETTINGS:{
 216 +               struct smi_settings *settings;
 217 +
 218 +               dev_info(inst->dev, "Reading SMI settings to user.");
 219 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 220 +               if (copy_to_user((void *)arg, settings,
 221 +                                sizeof(struct smi_settings)))
 222 +                       dev_err(inst->dev, "settings copy failed.");
 223 +               break;
 224 +       }
 225 +       case BCM2835_SMI_IOC_WRITE_SETTINGS:{
 226 +               struct smi_settings *settings;
 227 +
 228 +               dev_info(inst->dev, "Setting user's SMI settings.");
 229 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 230 +               if (copy_from_user(settings, (void *)arg,
 231 +                                  sizeof(struct smi_settings)))
 232 +                       dev_err(inst->dev, "settings copy failed.");
 233 +               else
 234 +                       bcm2835_smi_set_regs_from_settings(smi_inst);
 235 +               break;
 236 +       }
 237 +       case BCM2835_SMI_IOC_ADDRESS:
 238 +               dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg);
 239 +               bcm2835_smi_set_address(smi_inst, arg);
 240 +               break;
 241 +       default:
 242 +               dev_err(inst->dev, "invalid ioctl cmd: %d", cmd);
 243 +               ret = -ENOTTY;
 244 +               break;
 245 +       }
 246 +
 247 +       return ret;
 248 +}
 249 +
 250 +static int bcm2835_smi_open(struct inode *inode, struct file *file)
 251 +{
 252 +       int dev = iminor(inode);
 253 +
 254 +       dev_dbg(inst->dev, "SMI device opened.");
 255 +
 256 +       if (dev != DEVICE_MINOR) {
 257 +               dev_err(inst->dev,
 258 +                       "bcm2835_smi_release: Unknown minor device: %d",
 259 +                       dev);
 260 +               return -ENXIO;
 261 +       }
 262 +
 263 +       return 0;
 264 +}
 265 +
 266 +static int bcm2835_smi_release(struct inode *inode, struct file *file)
 267 +{
 268 +       int dev = iminor(inode);
 269 +
 270 +       if (dev != DEVICE_MINOR) {
 271 +               dev_err(inst->dev,
 272 +                       "bcm2835_smi_release: Unknown minor device %d", dev);
 273 +               return -ENXIO;
 274 +       }
 275 +
 276 +       return 0;
 277 +}
 278 +
 279 +static ssize_t dma_bounce_user(
 280 +       enum dma_transfer_direction dma_dir,
 281 +       char __user *user_ptr,
 282 +       size_t count,
 283 +       struct bcm2835_smi_bounce_info *bounce)
 284 +{
 285 +       int chunk_size;
 286 +       int chunk_no = 0;
 287 +       int count_left = count;
 288 +
 289 +       while (count_left) {
 290 +               int rv;
 291 +               void *buf;
 292 +
 293 +               /* Wait for current chunk to complete: */
 294 +               if (down_timeout(&bounce->callback_sem,
 295 +                       msecs_to_jiffies(1000))) {
 296 +                       dev_err(inst->dev, "DMA bounce timed out");
 297 +                       count -= (count_left);
 298 +                       break;
 299 +               }
 300 +
 301 +               if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)
 302 +                       dev_err(inst->dev, "WARNING: Ring buffer overflow");
 303 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
 304 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
 305 +               buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
 306 +               if (dma_dir == DMA_DEV_TO_MEM)
 307 +                       rv = copy_to_user(user_ptr, buf, chunk_size);
 308 +               else
 309 +                       rv = copy_from_user(buf, user_ptr, chunk_size);
 310 +               if (rv)
 311 +                       dev_err(inst->dev, "copy_*_user() failed!: %d", rv);
 312 +               user_ptr += chunk_size;
 313 +               count_left -= chunk_size;
 314 +               chunk_no++;
 315 +       }
 316 +       return count;
 317 +}
 318 +
 319 +static ssize_t
 320 +bcm2835_read_file(struct file *f, char __user *user_ptr,
 321 +                 size_t count, loff_t *offs)
 322 +{
 323 +       int odd_bytes;
 324 +
 325 +       dev_dbg(inst->dev, "User reading %zu bytes from SMI.", count);
 326 +       /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */
 327 +       if (count > DMA_THRESHOLD_BYTES)
 328 +               odd_bytes = count & 0x3;
 329 +       else
 330 +               odd_bytes = count;
 331 +       count -= odd_bytes;
 332 +       if (count) {
 333 +               struct bcm2835_smi_bounce_info *bounce;
 334 +
 335 +               count = bcm2835_smi_user_dma(smi_inst,
 336 +                       DMA_DEV_TO_MEM, user_ptr, count,
 337 +                       &bounce);
 338 +               if (count)
 339 +                       count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,
 340 +                               count, bounce);
 341 +       }
 342 +       if (odd_bytes) {
 343 +               /* Read from FIFO directly if not using DMA */
 344 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 345 +
 346 +               bcm2835_smi_read_buf(smi_inst, buf, odd_bytes);
 347 +               if (copy_to_user(user_ptr, buf, odd_bytes))
 348 +                       dev_err(inst->dev, "copy_to_user() failed.");
 349 +               count += odd_bytes;
 350 +
 351 +       }
 352 +       return count;
 353 +}
 354 +
 355 +static ssize_t
 356 +bcm2835_write_file(struct file *f, const char __user *user_ptr,
 357 +                  size_t count, loff_t *offs)
 358 +{
 359 +       int odd_bytes;
 360 +
 361 +       dev_dbg(inst->dev, "User writing %zu bytes to SMI.", count);
 362 +       if (count > DMA_THRESHOLD_BYTES)
 363 +               odd_bytes = count & 0x3;
 364 +       else
 365 +               odd_bytes = count;
 366 +       count -= odd_bytes;
 367 +       if (count) {
 368 +               struct bcm2835_smi_bounce_info *bounce;
 369 +
 370 +               count = bcm2835_smi_user_dma(smi_inst,
 371 +                       DMA_MEM_TO_DEV, (char __user *)user_ptr, count,
 372 +                       &bounce);
 373 +               if (count)
 374 +                       count = dma_bounce_user(DMA_MEM_TO_DEV,
 375 +                               (char __user *)user_ptr,
 376 +                               count, bounce);
 377 +       }
 378 +       if (odd_bytes) {
 379 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 380 +
 381 +               if (copy_from_user(buf, user_ptr, odd_bytes))
 382 +                       dev_err(inst->dev, "copy_from_user() failed.");
 383 +               else
 384 +                       bcm2835_smi_write_buf(smi_inst, buf, odd_bytes);
 385 +               count += odd_bytes;
 386 +       }
 387 +       return count;
 388 +}
 389 +
 390 +static const struct file_operations
 391 +bcm2835_smi_fops = {
 392 +       .owner = THIS_MODULE,
 393 +       .unlocked_ioctl = bcm2835_smi_ioctl,
 394 +       .open = bcm2835_smi_open,
 395 +       .release = bcm2835_smi_release,
 396 +       .read = bcm2835_read_file,
 397 +       .write = bcm2835_write_file,
 398 +};
 399 +
 400 +
 401 +/****************************************************************************
 402 +*
 403 +*   bcm2835_smi_probe - called when the driver is loaded.
 404 +*
 405 +***************************************************************************/
 406 +
 407 +static int bcm2835_smi_dev_probe(struct platform_device *pdev)
 408 +{
 409 +       int err;
 410 +       void *ptr_err;
 411 +       struct device *dev = &pdev->dev;
 412 +       struct device_node *node = dev->of_node, *smi_node;
 413 +
 414 +       if (!node) {
 415 +               dev_err(dev, "No device tree node supplied!");
 416 +               return -EINVAL;
 417 +       }
 418 +
 419 +       smi_node = of_parse_phandle(node, "smi_handle", 0);
 420 +
 421 +       if (!smi_node) {
 422 +               dev_err(dev, "No such property: smi_handle");
 423 +               return -ENXIO;
 424 +       }
 425 +
 426 +       smi_inst = bcm2835_smi_get(smi_node);
 427 +
 428 +       if (!smi_inst)
 429 +               return -EPROBE_DEFER;
 430 +
 431 +       /* Allocate buffers and instance data */
 432 +
 433 +       inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
 434 +
 435 +       if (!inst)
 436 +               return -ENOMEM;
 437 +
 438 +       inst->dev = dev;
 439 +
 440 +       /* Create character device entries */
 441 +
 442 +       err = alloc_chrdev_region(&bcm2835_smi_devid,
 443 +                                 DEVICE_MINOR, 1, DEVICE_NAME);
 444 +       if (err != 0) {
 445 +               dev_err(inst->dev, "unable to allocate device number");
 446 +               return -ENOMEM;
 447 +       }
 448 +       cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);
 449 +       bcm2835_smi_cdev.owner = THIS_MODULE;
 450 +       err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);
 451 +       if (err != 0) {
 452 +               dev_err(inst->dev, "unable to register device");
 453 +               err = -ENOMEM;
 454 +               goto failed_cdev_add;
 455 +       }
 456 +
 457 +       /* Create sysfs entries */
 458 +
 459 +       bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);
 460 +       ptr_err = bcm2835_smi_class;
 461 +       if (IS_ERR(ptr_err))
 462 +               goto failed_class_create;
 463 +
 464 +       bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,
 465 +                                       bcm2835_smi_devid, NULL,
 466 +                                       "smi");
 467 +       ptr_err = bcm2835_smi_dev;
 468 +       if (IS_ERR(ptr_err))
 469 +               goto failed_device_create;
 470 +
 471 +       dev_info(inst->dev, "initialised");
 472 +
 473 +       return 0;
 474 +
 475 +failed_device_create:
 476 +       class_destroy(bcm2835_smi_class);
 477 +failed_class_create:
 478 +       cdev_del(&bcm2835_smi_cdev);
 479 +       err = PTR_ERR(ptr_err);
 480 +failed_cdev_add:
 481 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 482 +       dev_err(dev, "could not load bcm2835_smi_dev");
 483 +       return err;
 484 +}
 485 +
 486 +/****************************************************************************
 487 +*
 488 +*   bcm2835_smi_remove - called when the driver is unloaded.
 489 +*
 490 +***************************************************************************/
 491 +
 492 +static int bcm2835_smi_dev_remove(struct platform_device *pdev)
 493 +{
 494 +       device_destroy(bcm2835_smi_class, bcm2835_smi_devid);
 495 +       class_destroy(bcm2835_smi_class);
 496 +       cdev_del(&bcm2835_smi_cdev);
 497 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 498 +
 499 +       dev_info(inst->dev, "SMI character dev removed - OK");
 500 +       return 0;
 501 +}
 502 +
 503 +/****************************************************************************
 504 +*
 505 +*   Register the driver with device tree
 506 +*
 507 +***************************************************************************/
 508 +
 509 +static const struct of_device_id bcm2835_smi_dev_of_match[] = {
 510 +       {.compatible = "brcm,bcm2835-smi-dev",},
 511 +       { /* sentinel */ },
 512 +};
 513 +
 514 +MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);
 515 +
 516 +static struct platform_driver bcm2835_smi_dev_driver = {
 517 +       .probe = bcm2835_smi_dev_probe,
 518 +       .remove = bcm2835_smi_dev_remove,
 519 +       .driver = {
 520 +                  .name = DRIVER_NAME,
 521 +                  .owner = THIS_MODULE,
 522 +                  .of_match_table = bcm2835_smi_dev_of_match,
 523 +                  },
 524 +};
 525 +
 526 +module_platform_driver(bcm2835_smi_dev_driver);
 527 +
 528 +MODULE_ALIAS("platform:smi-dev-bcm2835");
 529 +MODULE_LICENSE("GPL");
 530 +MODULE_DESCRIPTION(
 531 +       "Character device driver for BCM2835's secondary memory interface");
 532 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
 533 --- a/drivers/misc/Kconfig
 534 +++ b/drivers/misc/Kconfig
 535 @@ -10,6 +10,14 @@ config SENSORS_LIS3LV02D
 536         depends on INPUT
 537         select INPUT_POLLDEV
 538
 539 +config BCM2835_SMI
 540 +       tristate "Broadcom 283x Secondary Memory Interface driver"
 541 +       depends on ARCH_BCM2835
 542 +       default m
 543 +       help
 544 +               Driver for enabling and using Broadcom's Secondary/Slow Memory Interface.
 545 +               Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h
 546 +
 547  config AD525X_DPOT
 548         tristate "Analog Devices Digital Potentiometers"
 549         depends on (I2C || SPI) && SYSFS
 550 --- a/drivers/misc/Makefile
 551 +++ b/drivers/misc/Makefile
 552 @@ -11,6 +11,7 @@ obj-$(CONFIG_AD525X_DPOT_SPI) += ad525x_
 553  obj-$(CONFIG_INTEL_MID_PTI)    += pti.o
 554  obj-$(CONFIG_ATMEL_SSC)                += atmel-ssc.o
 555  obj-$(CONFIG_ATMEL_TCLIB)      += atmel_tclib.o
 556 +obj-$(CONFIG_BCM2835_SMI)      += bcm2835_smi.o
 557  obj-$(CONFIG_DUMMY_IRQ)                += dummy-irq.o
 558  obj-$(CONFIG_ICS932S401)       += ics932s401.o
 559  obj-$(CONFIG_LKDTM)            += lkdtm/
 560 --- /dev/null
 561 +++ b/drivers/misc/bcm2835_smi.c
 562 @@ -0,0 +1,955 @@
 563 +/**
 564 + * Broadcom Secondary Memory Interface driver
 565 + *
 566 + * Written by Luke Wren <luke@raspberrypi.org>
 567 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 568 + *
 569 + * Redistribution and use in source and binary forms, with or without
 570 + * modification, are permitted provided that the following conditions
 571 + * are met:
 572 + * 1. Redistributions of source code must retain the above copyright
 573 + *    notice, this list of conditions, and the following disclaimer,
 574 + *    without modification.
 575 + * 2. Redistributions in binary form must reproduce the above copyright
 576 + *    notice, this list of conditions and the following disclaimer in the
 577 + *    documentation and/or other materials provided with the distribution.
 578 + * 3. The names of the above-listed copyright holders may not be used
 579 + *    to endorse or promote products derived from this software without
 580 + *    specific prior written permission.
 581 + *
 582 + * ALTERNATIVELY, this software may be distributed under the terms of the
 583 + * GNU General Public License ("GPL") version 2, as published by the Free
 584 + * Software Foundation.
 585 + *
 586 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 587 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 588 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 589 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 590 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 591 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 592 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 593 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 594 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 595 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 596 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 597 + */
 598 +
 599 +#include <linux/clk.h>
 600 +#include <linux/kernel.h>
 601 +#include <linux/module.h>
 602 +#include <linux/of.h>
 603 +#include <linux/platform_device.h>
 604 +#include <linux/of_address.h>
 605 +#include <linux/of_platform.h>
 606 +#include <linux/mm.h>
 607 +#include <linux/slab.h>
 608 +#include <linux/pagemap.h>
 609 +#include <linux/dma-mapping.h>
 610 +#include <linux/dmaengine.h>
 611 +#include <linux/semaphore.h>
 612 +#include <linux/spinlock.h>
 613 +#include <linux/io.h>
 614 +
 615 +#define BCM2835_SMI_IMPLEMENTATION
 616 +#include <linux/broadcom/bcm2835_smi.h>
 617 +
 618 +#define DRIVER_NAME "smi-bcm2835"
 619 +
 620 +#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE)
 621 +
 622 +#define DMA_WRITE_TO_MEM true
 623 +#define DMA_READ_FROM_MEM false
 624 +
 625 +struct bcm2835_smi_instance {
 626 +       struct device *dev;
 627 +       struct smi_settings settings;
 628 +       __iomem void *smi_regs_ptr;
 629 +       dma_addr_t smi_regs_busaddr;
 630 +
 631 +       struct dma_chan *dma_chan;
 632 +       struct dma_slave_config dma_config;
 633 +
 634 +       struct bcm2835_smi_bounce_info bounce;
 635 +
 636 +       struct scatterlist buffer_sgl;
 637 +
 638 +       struct clk *clk;
 639 +
 640 +       /* Sometimes we are called into in an atomic context (e.g. by
 641 +          JFFS2 + MTD) so we can't use a mutex */
 642 +       spinlock_t transaction_lock;
 643 +};
 644 +
 645 +/****************************************************************************
 646 +*
 647 +*   SMI peripheral setup
 648 +*
 649 +***************************************************************************/
 650 +
 651 +static inline void write_smi_reg(struct bcm2835_smi_instance *inst,
 652 +       u32 val, unsigned reg)
 653 +{
 654 +       writel(val, inst->smi_regs_ptr + reg);
 655 +}
 656 +
 657 +static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg)
 658 +{
 659 +       return readl(inst->smi_regs_ptr + reg);
 660 +}
 661 +
 662 +/* Token-paste macro for e.g SMIDSR_RSTROBE ->  value of SMIDSR_RSTROBE_MASK */
 663 +#define _CONCAT(x, y) x##y
 664 +#define CONCAT(x, y) _CONCAT(x, y)
 665 +
 666 +#define SET_BIT_FIELD(dest, field, bits) ((dest) = \
 667 +       ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \
 668 +        CONCAT(field, _MASK)))
 669 +#define GET_BIT_FIELD(src, field) (((src) & \
 670 +       CONCAT(field, _MASK)) >> CONCAT(field, _OFFS))
 671 +
 672 +static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst,
 673 +       const char *label)
 674 +{
 675 +       dev_err(inst->dev, "SMI context dump: %s", label);
 676 +       dev_err(inst->dev, "SMICS:  0x%08x", read_smi_reg(inst, SMICS));
 677 +       dev_err(inst->dev, "SMIL:   0x%08x", read_smi_reg(inst, SMIL));
 678 +       dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0));
 679 +       dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0));
 680 +       dev_err(inst->dev, "SMIDC:  0x%08x", read_smi_reg(inst, SMIDC));
 681 +       dev_err(inst->dev, "SMIFD:  0x%08x", read_smi_reg(inst, SMIFD));
 682 +       dev_err(inst->dev, " ");
 683 +}
 684 +
 685 +static inline void smi_dump_context(struct bcm2835_smi_instance *inst)
 686 +{
 687 +       smi_dump_context_labelled(inst, "");
 688 +}
 689 +
 690 +static void smi_get_default_settings(struct bcm2835_smi_instance *inst)
 691 +{
 692 +       struct smi_settings *settings = &inst->settings;
 693 +
 694 +       settings->data_width = SMI_WIDTH_16BIT;
 695 +       settings->pack_data = true;
 696 +
 697 +       settings->read_setup_time = 1;
 698 +       settings->read_hold_time = 1;
 699 +       settings->read_pace_time = 1;
 700 +       settings->read_strobe_time = 3;
 701 +
 702 +       settings->write_setup_time = settings->read_setup_time;
 703 +       settings->write_hold_time = settings->read_hold_time;
 704 +       settings->write_pace_time = settings->read_pace_time;
 705 +       settings->write_strobe_time = settings->read_strobe_time;
 706 +
 707 +       settings->dma_enable = true;
 708 +       settings->dma_passthrough_enable = false;
 709 +       settings->dma_read_thresh = 0x01;
 710 +       settings->dma_write_thresh = 0x3f;
 711 +       settings->dma_panic_read_thresh = 0x20;
 712 +       settings->dma_panic_write_thresh = 0x20;
 713 +}
 714 +
 715 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst)
 716 +{
 717 +       struct smi_settings *settings = &inst->settings;
 718 +       int smidsr_temp = 0, smidsw_temp = 0, smics_temp,
 719 +           smidcs_temp, smidc_temp = 0;
 720 +
 721 +       spin_lock(&inst->transaction_lock);
 722 +
 723 +       /* temporarily disable the peripheral: */
 724 +       smics_temp = read_smi_reg(inst, SMICS);
 725 +       write_smi_reg(inst, 0, SMICS);
 726 +       smidcs_temp = read_smi_reg(inst, SMIDCS);
 727 +       write_smi_reg(inst, 0, SMIDCS);
 728 +
 729 +       if (settings->pack_data)
 730 +               smics_temp |= SMICS_PXLDAT;
 731 +       else
 732 +               smics_temp &= ~SMICS_PXLDAT;
 733 +
 734 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width);
 735 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time);
 736 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time);
 737 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time);
 738 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time);
 739 +       write_smi_reg(inst, smidsr_temp, SMIDSR0);
 740 +
 741 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width);
 742 +       if (settings->data_width == SMI_WIDTH_8BIT)
 743 +               smidsw_temp |= SMIDSW_WSWAP;
 744 +       else
 745 +               smidsw_temp &= ~SMIDSW_WSWAP;
 746 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time);
 747 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time);
 748 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time);
 749 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE,
 750 +                       settings->write_strobe_time);
 751 +       write_smi_reg(inst, smidsw_temp, SMIDSW0);
 752 +
 753 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh);
 754 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh);
 755 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICR,
 756 +                     settings->dma_panic_read_thresh);
 757 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICW,
 758 +                     settings->dma_panic_write_thresh);
 759 +       if (settings->dma_passthrough_enable) {
 760 +               smidc_temp |= SMIDC_DMAP;
 761 +               smidsr_temp |= SMIDSR_RDREQ;
 762 +               write_smi_reg(inst, smidsr_temp, SMIDSR0);
 763 +               smidsw_temp |= SMIDSW_WDREQ;
 764 +               write_smi_reg(inst, smidsw_temp, SMIDSW0);
 765 +       } else
 766 +               smidc_temp &= ~SMIDC_DMAP;
 767 +       if (settings->dma_enable)
 768 +               smidc_temp |= SMIDC_DMAEN;
 769 +       else
 770 +               smidc_temp &= ~SMIDC_DMAEN;
 771 +
 772 +       write_smi_reg(inst, smidc_temp, SMIDC);
 773 +
 774 +       /* re-enable (if was previously enabled) */
 775 +       write_smi_reg(inst, smics_temp, SMICS);
 776 +       write_smi_reg(inst, smidcs_temp, SMIDCS);
 777 +
 778 +       spin_unlock(&inst->transaction_lock);
 779 +}
 780 +EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings);
 781 +
 782 +struct smi_settings *bcm2835_smi_get_settings_from_regs
 783 +       (struct bcm2835_smi_instance *inst)
 784 +{
 785 +       struct smi_settings *settings = &inst->settings;
 786 +       int smidsr, smidsw, smidc;
 787 +
 788 +       spin_lock(&inst->transaction_lock);
 789 +
 790 +       smidsr = read_smi_reg(inst, SMIDSR0);
 791 +       smidsw = read_smi_reg(inst, SMIDSW0);
 792 +       smidc = read_smi_reg(inst, SMIDC);
 793 +
 794 +       settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ?
 795 +           true : false;
 796 +
 797 +       settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH);
 798 +       settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP);
 799 +       settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD);
 800 +       settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE);
 801 +       settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE);
 802 +
 803 +       settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP);
 804 +       settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD);
 805 +       settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE);
 806 +       settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE);
 807 +
 808 +       settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR);
 809 +       settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW);
 810 +       settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR);
 811 +       settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW);
 812 +       settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false;
 813 +       settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false;
 814 +
 815 +       spin_unlock(&inst->transaction_lock);
 816 +
 817 +       return settings;
 818 +}
 819 +EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs);
 820 +
 821 +static inline void smi_set_address(struct bcm2835_smi_instance *inst,
 822 +       unsigned int address)
 823 +{
 824 +       int smia_temp = 0, smida_temp = 0;
 825 +
 826 +       SET_BIT_FIELD(smia_temp, SMIA_ADDR, address);
 827 +       SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address);
 828 +
 829 +       /* Write to both address registers - user doesn't care whether we're
 830 +          doing programmed or direct transfers. */
 831 +       write_smi_reg(inst, smia_temp, SMIA);
 832 +       write_smi_reg(inst, smida_temp, SMIDA);
 833 +}
 834 +
 835 +static void smi_setup_regs(struct bcm2835_smi_instance *inst)
 836 +{
 837 +
 838 +       dev_dbg(inst->dev, "Initialising SMI registers...");
 839 +       /* Disable the peripheral if already enabled */
 840 +       write_smi_reg(inst, 0, SMICS);
 841 +       write_smi_reg(inst, 0, SMIDCS);
 842 +
 843 +       smi_get_default_settings(inst);
 844 +       bcm2835_smi_set_regs_from_settings(inst);
 845 +       smi_set_address(inst, 0);
 846 +
 847 +       write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS);
 848 +       write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE,
 849 +               SMIDCS);
 850 +}
 851 +
 852 +/****************************************************************************
 853 +*
 854 +*   Low-level SMI access functions
 855 +*   Other modules should use the exported higher-level functions e.g.
 856 +*   bcm2835_smi_write_buf() unless they have a good reason to use these
 857 +*
 858 +***************************************************************************/
 859 +
 860 +static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst)
 861 +{
 862 +       int timeout = 0;
 863 +
 864 +       write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS);
 865 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS);
 866 +       /* Make sure things happen in the right order...*/
 867 +       mb();
 868 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
 869 +               ++timeout < 10000)
 870 +               ;
 871 +       if (timeout < 10000)
 872 +               return read_smi_reg(inst, SMIDD);
 873 +
 874 +       dev_err(inst->dev,
 875 +               "SMI direct read timed out (is the clock set up correctly?)");
 876 +       return 0;
 877 +}
 878 +
 879 +static inline void smi_write_single_word(struct bcm2835_smi_instance *inst,
 880 +       uint32_t data)
 881 +{
 882 +       int timeout = 0;
 883 +
 884 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS);
 885 +       write_smi_reg(inst, data, SMIDD);
 886 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START,
 887 +               SMIDCS);
 888 +
 889 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
 890 +               ++timeout < 10000)
 891 +               ;
 892 +       if (timeout >= 10000)
 893 +               dev_err(inst->dev,
 894 +               "SMI direct write timed out (is the clock set up correctly?)");
 895 +}
 896 +
 897 +/* Initiates a programmed read into the read FIFO. It is up to the caller to
 898 + * read data from the FIFO -  either via paced DMA transfer,
 899 + * or polling SMICS_RXD to check whether data is available.
 900 + * SMICS_ACTIVE will go low upon completion. */
 901 +static void smi_init_programmed_read(struct bcm2835_smi_instance *inst,
 902 +       int num_transfers)
 903 +{
 904 +       int smics_temp;
 905 +
 906 +       /* Disable the peripheral: */
 907 +       smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);
 908 +       write_smi_reg(inst, smics_temp, SMICS);
 909 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
 910 +               ;
 911 +
 912 +       /* Program the transfer count: */
 913 +       write_smi_reg(inst, num_transfers, SMIL);
 914 +
 915 +       /* re-enable and start: */
 916 +       smics_temp |= SMICS_ENABLE;
 917 +       write_smi_reg(inst, smics_temp, SMICS);
 918 +       smics_temp |= SMICS_CLEAR;
 919 +       /* Just to be certain: */
 920 +       mb();
 921 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
 922 +               ;
 923 +       write_smi_reg(inst, smics_temp, SMICS);
 924 +       smics_temp |= SMICS_START;
 925 +       write_smi_reg(inst, smics_temp, SMICS);
 926 +}
 927 +
 928 +/* Initiates a programmed write sequence, using data from the write FIFO.
 929 + * It is up to the caller to initiate a DMA transfer before calling,
 930 + * or use another method to keep the write FIFO topped up.
 931 + * SMICS_ACTIVE will go low upon completion.
 932 + */
 933 +static void smi_init_programmed_write(struct bcm2835_smi_instance *inst,
 934 +       int num_transfers)
 935 +{
 936 +       int smics_temp;
 937 +
 938 +       /* Disable the peripheral: */
 939 +       smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
 940 +       write_smi_reg(inst, smics_temp, SMICS);
 941 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
 942 +               ;
 943 +
 944 +       /* Program the transfer count: */
 945 +       write_smi_reg(inst, num_transfers, SMIL);
 946 +
 947 +       /* setup, re-enable and start: */
 948 +       smics_temp |= SMICS_WRITE | SMICS_ENABLE;
 949 +       write_smi_reg(inst, smics_temp, SMICS);
 950 +       smics_temp |= SMICS_START;
 951 +       write_smi_reg(inst, smics_temp, SMICS);
 952 +}
 953 +
 954 +/* Initiate a read and then poll FIFO for data, reading out as it appears. */
 955 +static void smi_read_fifo(struct bcm2835_smi_instance *inst,
 956 +       uint32_t *dest, int n_bytes)
 957 +{
 958 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
 959 +               smi_dump_context_labelled(inst,
 960 +                       "WARNING: read FIFO not empty at start of read call.");
 961 +               while (read_smi_reg(inst, SMICS))
 962 +                       ;
 963 +       }
 964 +
 965 +       /* Dispatch the read: */
 966 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
 967 +               smi_init_programmed_read(inst, n_bytes);
 968 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
 969 +               smi_init_programmed_read(inst, n_bytes / 2);
 970 +       else {
 971 +               dev_err(inst->dev, "Unsupported data width for read.");
 972 +               return;
 973 +       }
 974 +
 975 +       /* Poll FIFO to keep it empty */
 976 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
 977 +               if (read_smi_reg(inst, SMICS) & SMICS_RXD)
 978 +                       *dest++ = read_smi_reg(inst, SMID);
 979 +
 980 +       /* Ensure that the FIFO is emptied */
 981 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
 982 +               int fifo_count;
 983 +
 984 +               fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD),
 985 +                       SMIFD_FCNT);
 986 +               while (fifo_count--)
 987 +                       *dest++ = read_smi_reg(inst, SMID);
 988 +       }
 989 +
 990 +       if (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
 991 +               smi_dump_context_labelled(inst,
 992 +                       "WARNING: transaction finished but done bit not set.");
 993 +
 994 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD)
 995 +               smi_dump_context_labelled(inst,
 996 +                       "WARNING: read FIFO not empty at end of read call.");
 997 +
 998 +}
 999 +
1000 +/* Initiate a write, and then keep the FIFO topped up. */
1001 +static void smi_write_fifo(struct bcm2835_smi_instance *inst,
1002 +       uint32_t *src, int n_bytes)
1003 +{
1004 +       int i, timeout = 0;
1005 +
1006 +       /* Empty FIFOs if not already so */
1007 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) {
1008 +               smi_dump_context_labelled(inst,
1009 +                   "WARNING: write fifo not empty at start of write call.");
1010 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR,
1011 +                       SMICS);
1012 +       }
1013 +
1014 +       /* Initiate the transfer */
1015 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1016 +               smi_init_programmed_write(inst, n_bytes);
1017 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1018 +               smi_init_programmed_write(inst, n_bytes / 2);
1019 +       else {
1020 +               dev_err(inst->dev, "Unsupported data width for write.");
1021 +               return;
1022 +       }
1023 +       /* Fill the FIFO: */
1024 +       for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) {
1025 +               while (!(read_smi_reg(inst, SMICS) & SMICS_TXD))
1026 +                       ;
1027 +               write_smi_reg(inst, *src++, SMID);
1028 +       }
1029 +       /* Busy wait... */
1030 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout <
1031 +               1000000)
1032 +               ;
1033 +       if (timeout >= 1000000)
1034 +               smi_dump_context_labelled(inst,
1035 +                       "Timed out on write operation!");
1036 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE))
1037 +               smi_dump_context_labelled(inst,
1038 +                       "WARNING: FIFO not empty at end of write operation.");
1039 +}
1040 +
1041 +/****************************************************************************
1042 +*
1043 +*   SMI DMA operations
1044 +*
1045 +***************************************************************************/
1046 +
1047 +/* Disable SMI and put it into the correct direction before doing DMA setup.
1048 +   Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */
1049 +static void smi_disable(struct bcm2835_smi_instance *inst,
1050 +       enum dma_transfer_direction direction)
1051 +{
1052 +       int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
1053 +
1054 +       if (direction == DMA_DEV_TO_MEM)
1055 +               smics_temp &= ~SMICS_WRITE;
1056 +       else
1057 +               smics_temp |= SMICS_WRITE;
1058 +       write_smi_reg(inst, smics_temp, SMICS);
1059 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1060 +               ;
1061 +}
1062 +
1063 +static struct scatterlist *smi_scatterlist_from_buffer(
1064 +       struct bcm2835_smi_instance *inst,
1065 +       dma_addr_t buf,
1066 +       size_t len,
1067 +       struct scatterlist *sg)
1068 +{
1069 +       sg_init_table(sg, 1);
1070 +       sg_dma_address(sg) = buf;
1071 +       sg_dma_len(sg) = len;
1072 +       return sg;
1073 +}
1074 +
1075 +static void smi_dma_callback_user_copy(void *param)
1076 +{
1077 +       /* Notify the bottom half that a chunk is ready for user copy */
1078 +       struct bcm2835_smi_instance *inst =
1079 +               (struct bcm2835_smi_instance *)param;
1080 +
1081 +       up(&inst->bounce.callback_sem);
1082 +}
1083 +
1084 +/* Creates a descriptor, assigns the given callback, and submits the
1085 +   descriptor to dmaengine. Does not block - can queue up multiple
1086 +   descriptors and then wait for them all to complete.
1087 +   sg_len is the number of control blocks, NOT the number of bytes.
1088 +   dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM.
1089 +   callback can be NULL - in this case it is not called. */
1090 +static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl(
1091 +       struct bcm2835_smi_instance *inst,
1092 +       struct scatterlist *sgl,
1093 +       size_t sg_len,
1094 +       enum dma_transfer_direction dir,
1095 +       dma_async_tx_callback callback)
1096 +{
1097 +       struct dma_async_tx_descriptor *desc;
1098 +
1099 +       desc = dmaengine_prep_slave_sg(inst->dma_chan,
1100 +                                      sgl,
1101 +                                      sg_len,
1102 +                                      dir,
1103 +                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK |
1104 +                                      DMA_PREP_FENCE);
1105 +       if (!desc) {
1106 +               dev_err(inst->dev, "read_sgl: dma slave preparation failed!");
1107 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE,
1108 +                       SMICS);
1109 +               while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1110 +                       cpu_relax();
1111 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE,
1112 +                       SMICS);
1113 +               return NULL;
1114 +       }
1115 +       desc->callback = callback;
1116 +       desc->callback_param = inst;
1117 +       if (dmaengine_submit(desc) < 0)
1118 +               return NULL;
1119 +       return desc;
1120 +}
1121 +
1122 +/* NB this function blocks until the transfer is complete */
1123 +static void
1124 +smi_dma_read_sgl(struct bcm2835_smi_instance *inst,
1125 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1126 +{
1127 +       struct dma_async_tx_descriptor *desc;
1128 +
1129 +       /* Disable SMI and set to read before dispatching DMA - if SMI is in
1130 +        * write mode and TX fifo is empty, it will generate a DREQ which may
1131 +        * cause the read DMA to complete before the SMI read command is even
1132 +        * dispatched! We want to dispatch DMA before SMI read so that reading
1133 +        * is gapless, for logic analyser.
1134 +        */
1135 +
1136 +       smi_disable(inst, DMA_DEV_TO_MEM);
1137 +
1138 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL);
1139 +       dma_async_issue_pending(inst->dma_chan);
1140 +
1141 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1142 +               smi_init_programmed_read(inst, n_bytes);
1143 +       else
1144 +               smi_init_programmed_read(inst, n_bytes / 2);
1145 +
1146 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1147 +               smi_dump_context_labelled(inst, "DMA timeout!");
1148 +}
1149 +
1150 +static void
1151 +smi_dma_write_sgl(struct bcm2835_smi_instance *inst,
1152 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1153 +{
1154 +       struct dma_async_tx_descriptor *desc;
1155 +
1156 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1157 +               smi_init_programmed_write(inst, n_bytes);
1158 +       else
1159 +               smi_init_programmed_write(inst, n_bytes / 2);
1160 +
1161 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL);
1162 +       dma_async_issue_pending(inst->dma_chan);
1163 +
1164 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1165 +               smi_dump_context_labelled(inst, "DMA timeout!");
1166 +       else
1167 +               /* Wait for SMI to finish our writes */
1168 +               while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1169 +                       cpu_relax();
1170 +}
1171 +
1172 +ssize_t bcm2835_smi_user_dma(
1173 +       struct bcm2835_smi_instance *inst,
1174 +       enum dma_transfer_direction dma_dir,
1175 +       char __user *user_ptr, size_t count,
1176 +       struct bcm2835_smi_bounce_info **bounce)
1177 +{
1178 +       int chunk_no = 0, chunk_size, count_left = count;
1179 +       struct scatterlist *sgl;
1180 +       void (*init_trans_func)(struct bcm2835_smi_instance *, int);
1181 +
1182 +       spin_lock(&inst->transaction_lock);
1183 +
1184 +       if (dma_dir == DMA_DEV_TO_MEM)
1185 +               init_trans_func = smi_init_programmed_read;
1186 +       else
1187 +               init_trans_func = smi_init_programmed_write;
1188 +
1189 +       smi_disable(inst, dma_dir);
1190 +
1191 +       sema_init(&inst->bounce.callback_sem, 0);
1192 +       if (bounce)
1193 +               *bounce = &inst->bounce;
1194 +       while (count_left) {
1195 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
1196 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
1197 +               if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) {
1198 +                       sgl =
1199 +                       &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
1200 +               } else {
1201 +                       sgl = smi_scatterlist_from_buffer(
1202 +                               inst,
1203 +                               inst->bounce.phys[
1204 +                                       chunk_no % DMA_BOUNCE_BUFFER_COUNT],
1205 +                               chunk_size,
1206 +                               &inst->buffer_sgl);
1207 +               }
1208 +
1209 +               if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir,
1210 +                       smi_dma_callback_user_copy
1211 +               )) {
1212 +                       dev_err(inst->dev, "sgl submit failed");
1213 +                       count = 0;
1214 +                       goto out;
1215 +               }
1216 +               count_left -= chunk_size;
1217 +               chunk_no++;
1218 +       }
1219 +       dma_async_issue_pending(inst->dma_chan);
1220 +
1221 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1222 +               init_trans_func(inst, count);
1223 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1224 +               init_trans_func(inst, count / 2);
1225 +out:
1226 +       spin_unlock(&inst->transaction_lock);
1227 +       return count;
1228 +}
1229 +EXPORT_SYMBOL(bcm2835_smi_user_dma);
1230 +
1231 +
1232 +/****************************************************************************
1233 +*
1234 +*   High level buffer transfer functions - for use by other drivers
1235 +*
1236 +***************************************************************************/
1237 +
1238 +/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */
1239 +void bcm2835_smi_write_buf(
1240 +       struct bcm2835_smi_instance *inst,
1241 +       const void *buf, size_t n_bytes)
1242 +{
1243 +       int odd_bytes = n_bytes & 0x3;
1244 +
1245 +       n_bytes -= odd_bytes;
1246 +
1247 +       spin_lock(&inst->transaction_lock);
1248 +
1249 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1250 +               dma_addr_t phy_addr = dma_map_single(
1251 +                       inst->dev,
1252 +                       (void *)buf,
1253 +                       n_bytes,
1254 +                       DMA_MEM_TO_DEV);
1255 +               struct scatterlist *sgl =
1256 +                       smi_scatterlist_from_buffer(inst, phy_addr, n_bytes,
1257 +                               &inst->buffer_sgl);
1258 +
1259 +               if (!sgl) {
1260 +                       smi_dump_context_labelled(inst,
1261 +                       "Error: could not create scatterlist for write!");
1262 +                       goto out;
1263 +               }
1264 +               smi_dma_write_sgl(inst, sgl, 1, n_bytes);
1265 +
1266 +               dma_unmap_single
1267 +                       (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV);
1268 +       } else if (n_bytes) {
1269 +               smi_write_fifo(inst, (uint32_t *) buf, n_bytes);
1270 +       }
1271 +       buf += n_bytes;
1272 +
1273 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1274 +               while (odd_bytes--)
1275 +                       smi_write_single_word(inst, *(uint8_t *) (buf++));
1276 +       } else {
1277 +               while (odd_bytes >= 2) {
1278 +                       smi_write_single_word(inst, *(uint16_t *)buf);
1279 +                       buf += 2;
1280 +                       odd_bytes -= 2;
1281 +               }
1282 +               if (odd_bytes) {
1283 +                       /* Reading an odd number of bytes on a 16 bit bus is
1284 +                          a user bug. It's kinder to fail early and tell them
1285 +                          than to e.g. transparently give them the bottom byte
1286 +                          of a 16 bit transfer. */
1287 +                       dev_err(inst->dev,
1288 +               "WARNING: odd number of bytes specified for wide transfer.");
1289 +                       dev_err(inst->dev,
1290 +               "At least one byte dropped as a result.");
1291 +                       dump_stack();
1292 +               }
1293 +       }
1294 +out:
1295 +       spin_unlock(&inst->transaction_lock);
1296 +}
1297 +EXPORT_SYMBOL(bcm2835_smi_write_buf);
1298 +
1299 +void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst,
1300 +       void *buf, size_t n_bytes)
1301 +{
1302 +
1303 +       /* SMI is inherently 32-bit, which causes surprising amounts of mess
1304 +          for bytes % 4 != 0. Easiest to avoid this mess altogether
1305 +          by handling remainder separately. */
1306 +       int odd_bytes = n_bytes & 0x3;
1307 +
1308 +       spin_lock(&inst->transaction_lock);
1309 +       n_bytes -= odd_bytes;
1310 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1311 +               dma_addr_t phy_addr = dma_map_single(inst->dev,
1312 +                                                    buf, n_bytes,
1313 +                                                    DMA_DEV_TO_MEM);
1314 +               struct scatterlist *sgl = smi_scatterlist_from_buffer(
1315 +                       inst, phy_addr, n_bytes,
1316 +                       &inst->buffer_sgl);
1317 +               if (!sgl) {
1318 +                       smi_dump_context_labelled(inst,
1319 +                       "Error: could not create scatterlist for read!");
1320 +                       goto out;
1321 +               }
1322 +               smi_dma_read_sgl(inst, sgl, 1, n_bytes);
1323 +               dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM);
1324 +       } else if (n_bytes) {
1325 +               smi_read_fifo(inst, (uint32_t *)buf, n_bytes);
1326 +       }
1327 +       buf += n_bytes;
1328 +
1329 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1330 +               while (odd_bytes--)
1331 +                       *((uint8_t *) (buf++)) = smi_read_single_word(inst);
1332 +       } else {
1333 +               while (odd_bytes >= 2) {
1334 +                       *(uint16_t *) buf = smi_read_single_word(inst);
1335 +                       buf += 2;
1336 +                       odd_bytes -= 2;
1337 +               }
1338 +               if (odd_bytes) {
1339 +                       dev_err(inst->dev,
1340 +               "WARNING: odd number of bytes specified for wide transfer.");
1341 +                       dev_err(inst->dev,
1342 +               "At least one byte dropped as a result.");
1343 +                       dump_stack();
1344 +               }
1345 +       }
1346 +out:
1347 +       spin_unlock(&inst->transaction_lock);
1348 +}
1349 +EXPORT_SYMBOL(bcm2835_smi_read_buf);
1350 +
1351 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1352 +       unsigned int address)
1353 +{
1354 +       spin_lock(&inst->transaction_lock);
1355 +       smi_set_address(inst, address);
1356 +       spin_unlock(&inst->transaction_lock);
1357 +}
1358 +EXPORT_SYMBOL(bcm2835_smi_set_address);
1359 +
1360 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node)
1361 +{
1362 +       struct platform_device *pdev;
1363 +
1364 +       if (!node)
1365 +               return NULL;
1366 +
1367 +       pdev = of_find_device_by_node(node);
1368 +       if (!pdev)
1369 +               return NULL;
1370 +
1371 +       return platform_get_drvdata(pdev);
1372 +}
1373 +EXPORT_SYMBOL(bcm2835_smi_get);
1374 +
1375 +/****************************************************************************
1376 +*
1377 +*   bcm2835_smi_probe - called when the driver is loaded.
1378 +*
1379 +***************************************************************************/
1380 +
1381 +static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst)
1382 +{
1383 +       int i, rv = 0;
1384 +
1385 +       inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx");
1386 +
1387 +       inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1388 +       inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1389 +       inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID;
1390 +       inst->dma_config.dst_addr = inst->dma_config.src_addr;
1391 +       /* Direction unimportant - always overridden by prep_slave_sg */
1392 +       inst->dma_config.direction = DMA_DEV_TO_MEM;
1393 +       dmaengine_slave_config(inst->dma_chan, &inst->dma_config);
1394 +       /* Alloc and map bounce buffers */
1395 +       for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) {
1396 +               inst->bounce.buffer[i] =
1397 +               dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE,
1398 +                               &inst->bounce.phys[i],
1399 +                               GFP_KERNEL);
1400 +               if (!inst->bounce.buffer[i]) {
1401 +                       dev_err(inst->dev, "Could not allocate buffer!");
1402 +                       rv = -ENOMEM;
1403 +                       break;
1404 +               }
1405 +               smi_scatterlist_from_buffer(
1406 +                       inst,
1407 +                       inst->bounce.phys[i],
1408 +                       DMA_BOUNCE_BUFFER_SIZE,
1409 +                       &inst->bounce.sgl[i]
1410 +               );
1411 +       }
1412 +
1413 +       return rv;
1414 +}
1415 +
1416 +static int bcm2835_smi_probe(struct platform_device *pdev)
1417 +{
1418 +       int err;
1419 +       struct device *dev = &pdev->dev;
1420 +       struct device_node *node = dev->of_node;
1421 +       struct resource *ioresource;
1422 +       struct bcm2835_smi_instance *inst;
1423 +       const __be32 *addr;
1424 +
1425 +       /* We require device tree support */
1426 +       if (!node)
1427 +               return -EINVAL;
1428 +       /* Allocate buffers and instance data */
1429 +       inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),
1430 +               GFP_KERNEL);
1431 +       if (!inst)
1432 +               return -ENOMEM;
1433 +
1434 +       inst->dev = dev;
1435 +       spin_lock_init(&inst->transaction_lock);
1436 +
1437 +       ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1438 +       inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
1439 +       if (IS_ERR(inst->smi_regs_ptr)) {
1440 +               err = PTR_ERR(inst->smi_regs_ptr);
1441 +               goto err;
1442 +       }
1443 +       addr = of_get_address(node, 0, NULL, NULL);
1444 +       inst->smi_regs_busaddr = be32_to_cpu(*addr);
1445 +
1446 +       err = bcm2835_smi_dma_setup(inst);
1447 +       if (err)
1448 +               goto err;
1449 +
1450 +       /* request clock */
1451 +       inst->clk = devm_clk_get(dev, NULL);
1452 +       if (!inst->clk)
1453 +               goto err;
1454 +       clk_prepare_enable(inst->clk);
1455 +
1456 +       /* Finally, do peripheral setup */
1457 +       smi_setup_regs(inst);
1458 +
1459 +       platform_set_drvdata(pdev, inst);
1460 +
1461 +       dev_info(inst->dev, "initialised");
1462 +
1463 +       return 0;
1464 +err:
1465 +       kfree(inst);
1466 +       return err;
1467 +}
1468 +
1469 +/****************************************************************************
1470 +*
1471 +*   bcm2835_smi_remove - called when the driver is unloaded.
1472 +*
1473 +***************************************************************************/
1474 +
1475 +static int bcm2835_smi_remove(struct platform_device *pdev)
1476 +{
1477 +       struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);
1478 +       struct device *dev = inst->dev;
1479 +
1480 +       dmaengine_terminate_all(inst->dma_chan);
1481 +       dma_release_channel(inst->dma_chan);
1482 +
1483 +       clk_disable_unprepare(inst->clk);
1484 +
1485 +       dev_info(dev, "SMI device removed - OK");
1486 +       return 0;
1487 +}
1488 +
1489 +/****************************************************************************
1490 +*
1491 +*   Register the driver with device tree
1492 +*
1493 +***************************************************************************/
1494 +
1495 +static const struct of_device_id bcm2835_smi_of_match[] = {
1496 +       {.compatible = "brcm,bcm2835-smi",},
1497 +       { /* sentinel */ },
1498 +};
1499 +
1500 +MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match);
1501 +
1502 +static struct platform_driver bcm2835_smi_driver = {
1503 +       .probe = bcm2835_smi_probe,
1504 +       .remove = bcm2835_smi_remove,
1505 +       .driver = {
1506 +                  .name = DRIVER_NAME,
1507 +                  .owner = THIS_MODULE,
1508 +                  .of_match_table = bcm2835_smi_of_match,
1509 +                  },
1510 +};
1511 +
1512 +module_platform_driver(bcm2835_smi_driver);
1513 +
1514 +MODULE_ALIAS("platform:smi-bcm2835");
1515 +MODULE_LICENSE("GPL");
1516 +MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface");
1517 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
1518 --- /dev/null
1519 +++ b/include/linux/broadcom/bcm2835_smi.h
1520 @@ -0,0 +1,391 @@
1521 +/**
1522 + * Declarations and definitions for Broadcom's Secondary Memory Interface
1523 + *
1524 + * Written by Luke Wren <luke@raspberrypi.org>
1525 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
1526 + * Copyright (c) 2010-2012 Broadcom. All rights reserved.
1527 + *
1528 + * Redistribution and use in source and binary forms, with or without
1529 + * modification, are permitted provided that the following conditions
1530 + * are met:
1531 + * 1. Redistributions of source code must retain the above copyright
1532 + *    notice, this list of conditions, and the following disclaimer,
1533 + *    without modification.
1534 + * 2. Redistributions in binary form must reproduce the above copyright
1535 + *    notice, this list of conditions and the following disclaimer in the
1536 + *    documentation and/or other materials provided with the distribution.
1537 + * 3. The names of the above-listed copyright holders may not be used
1538 + *    to endorse or promote products derived from this software without
1539 + *    specific prior written permission.
1540 + *
1541 + * ALTERNATIVELY, this software may be distributed under the terms of the
1542 + * GNU General Public License ("GPL") version 2, as published by the Free
1543 + * Software Foundation.
1544 + *
1545 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
1546 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
1547 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
1548 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
1549 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
1550 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
1551 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
1552 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
1553 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
1554 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1555 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1556 + */
1557 +
1558 +#ifndef BCM2835_SMI_H
1559 +#define BCM2835_SMI_H
1560 +
1561 +#include <linux/ioctl.h>
1562 +
1563 +#ifndef __KERNEL__
1564 +#include <stdint.h>
1565 +#include <stdbool.h>
1566 +#endif
1567 +
1568 +#define BCM2835_SMI_IOC_MAGIC 0x1
1569 +#define BCM2835_SMI_INVALID_HANDLE (~0)
1570 +
1571 +/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
1572 +#define BCM2835_SMI_IOC_GET_SETTINGS    _IO(BCM2835_SMI_IOC_MAGIC, 0)
1573 +#define BCM2835_SMI_IOC_WRITE_SETTINGS  _IO(BCM2835_SMI_IOC_MAGIC, 1)
1574 +#define BCM2835_SMI_IOC_ADDRESS         _IO(BCM2835_SMI_IOC_MAGIC, 2)
1575 +#define BCM2835_SMI_IOC_MAX         2
1576 +
1577 +#define SMI_WIDTH_8BIT 0
1578 +#define SMI_WIDTH_16BIT 1
1579 +#define SMI_WIDTH_9BIT 2
1580 +#define SMI_WIDTH_18BIT 3
1581 +
1582 +/* max number of bytes where DMA will not be used */
1583 +#define DMA_THRESHOLD_BYTES 128
1584 +#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
1585 +#define DMA_BOUNCE_BUFFER_COUNT 3
1586 +
1587 +
1588 +struct smi_settings {
1589 +       int data_width;
1590 +       /* Whether or not to pack multiple SMI transfers into a
1591 +          single 32 bit FIFO word */
1592 +       bool pack_data;
1593 +
1594 +       /* Timing for reads (writes the same but for WE)
1595 +        *
1596 +        * OE ----------+          +--------------------
1597 +        *              |          |
1598 +        *              +----------+
1599 +        * SD -<==============================>-----------
1600 +        * SA -<=========================================>-
1601 +        *    <-setup->  <-strobe ->  <-hold ->  <- pace ->
1602 +        */
1603 +
1604 +       int read_setup_time;
1605 +       int read_hold_time;
1606 +       int read_pace_time;
1607 +       int read_strobe_time;
1608 +
1609 +       int write_setup_time;
1610 +       int write_hold_time;
1611 +       int write_pace_time;
1612 +       int write_strobe_time;
1613 +
1614 +       bool dma_enable;                /* DREQs */
1615 +       bool dma_passthrough_enable;    /* External DREQs */
1616 +       int dma_read_thresh;
1617 +       int dma_write_thresh;
1618 +       int dma_panic_read_thresh;
1619 +       int dma_panic_write_thresh;
1620 +};
1621 +
1622 +/****************************************************************************
1623 +*
1624 +*   Declare exported SMI functions
1625 +*
1626 +***************************************************************************/
1627 +
1628 +#ifdef __KERNEL__
1629 +
1630 +#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
1631 +#include <linux/of.h>
1632 +#include <linux/semaphore.h>
1633 +
1634 +struct bcm2835_smi_instance;
1635 +
1636 +struct bcm2835_smi_bounce_info {
1637 +       struct semaphore callback_sem;
1638 +       void *buffer[DMA_BOUNCE_BUFFER_COUNT];
1639 +       dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
1640 +       struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
1641 +};
1642 +
1643 +
1644 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
1645 +
1646 +struct smi_settings *bcm2835_smi_get_settings_from_regs(
1647 +       struct bcm2835_smi_instance *inst);
1648 +
1649 +void bcm2835_smi_write_buf(
1650 +       struct bcm2835_smi_instance *inst,
1651 +       const void *buf,
1652 +       size_t n_bytes);
1653 +
1654 +void bcm2835_smi_read_buf(
1655 +       struct bcm2835_smi_instance *inst,
1656 +       void *buf,
1657 +       size_t n_bytes);
1658 +
1659 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1660 +       unsigned int address);
1661 +
1662 +ssize_t bcm2835_smi_user_dma(
1663 +       struct bcm2835_smi_instance *inst,
1664 +       enum dma_transfer_direction dma_dir,
1665 +       char __user *user_ptr,
1666 +       size_t count,
1667 +       struct bcm2835_smi_bounce_info **bounce);
1668 +
1669 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
1670 +
1671 +#endif /* __KERNEL__ */
1672 +
1673 +/****************************************************************
1674 +*
1675 +*      Implementation-only declarations
1676 +*
1677 +****************************************************************/
1678 +
1679 +#ifdef BCM2835_SMI_IMPLEMENTATION
1680 +
1681 +/* Clock manager registers for SMI clock: */
1682 +#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
1683 +/* Clock manager "password" to protect registers from spurious writes */
1684 +#define CM_PWD (0x5a << 24)
1685 +
1686 +#define CM_SMI_CTL     0x00
1687 +#define CM_SMI_DIV     0x04
1688 +
1689 +#define CM_SMI_CTL_FLIP (1 << 8)
1690 +#define CM_SMI_CTL_BUSY (1 << 7)
1691 +#define CM_SMI_CTL_KILL (1 << 5)
1692 +#define CM_SMI_CTL_ENAB (1 << 4)
1693 +#define CM_SMI_CTL_SRC_MASK (0xf)
1694 +#define CM_SMI_CTL_SRC_OFFS (0)
1695 +
1696 +#define CM_SMI_DIV_DIVI_MASK (0xf <<  12)
1697 +#define CM_SMI_DIV_DIVI_OFFS (12)
1698 +#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
1699 +#define CM_SMI_DIV_DIVF_OFFS (4)
1700 +
1701 +/* SMI register mapping:*/
1702 +#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
1703 +
1704 +#define SMICS  0x00    /* control + status register            */
1705 +#define SMIL   0x04    /* length/count (n external txfers)     */
1706 +#define SMIA   0x08    /* address register                     */
1707 +#define SMID   0x0c    /* data register                        */
1708 +#define SMIDSR0        0x10    /* device 0 read settings               */
1709 +#define SMIDSW0        0x14    /* device 0 write settings              */
1710 +#define SMIDSR1        0x18    /* device 1 read settings               */
1711 +#define SMIDSW1        0x1c    /* device 1 write settings              */
1712 +#define SMIDSR2        0x20    /* device 2 read settings               */
1713 +#define SMIDSW2        0x24    /* device 2 write settings              */
1714 +#define SMIDSR3        0x28    /* device 3 read settings               */
1715 +#define SMIDSW3        0x2c    /* device 3 write settings              */
1716 +#define SMIDC  0x30    /* DMA control registers                */
1717 +#define SMIDCS 0x34    /* direct control/status register       */
1718 +#define SMIDA  0x38    /* direct address register              */
1719 +#define SMIDD  0x3c    /* direct data registers                */
1720 +#define SMIFD  0x40    /* FIFO debug register                  */
1721 +
1722 +
1723 +
1724 +/* Control and Status register bits:
1725 + * SMICS_RXF   : RX fifo full: 1 when RX fifo is full
1726 + * SMICS_TXE   : TX fifo empty: 1 when empty.
1727 + * SMICS_RXD   : RX fifo contains data: 1 when there is data.
1728 + * SMICS_TXD   : TX fifo can accept data: 1 when true.
1729 + * SMICS_RXR   : RX fifo needs reading: 1 when fifo more than 3/4 full, or
1730 + *               when "DONE" and fifo not emptied.
1731 + * SMICS_TXW   : TX fifo needs writing: 1 when less than 1/4 full.
1732 + * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written
1733 + *               when full. Write 1 to clear.
1734 + * SMICS_EDREQ : 1 when external DREQ received.
1735 + * SMICS_PXLDAT        :  Pixel data:  write 1 to enable pixel transfer modes.
1736 + * SMICS_SETERR        : 1 if there was an error writing to setup regs (e.g.
1737 + *               tx was in progress). Write 1 to clear.
1738 + * SMICS_PVMODE        : Set to 1 to enable pixel valve mode.
1739 + * SMICS_INTR  : Set to 1 to enable interrupt on RX.
1740 + * SMICS_INTT  : Set to 1 to enable interrupt on TX.
1741 + * SMICS_INTD  : Set to 1 to enable interrupt on DONE condition.
1742 + * SMICS_TEEN  : Tear effect mode enabled: Programmed transfers will wait
1743 + *               for a TE trigger before writing.
1744 + * SMICS_PAD1  : Padding settings for external transfers. For writes: the
1745 + *               number of bytes initially written to  the TX fifo that
1746 + * SMICS_PAD0  : should be ignored. For reads: the number of bytes that will
1747 + *               be read before the data, and should be dropped.
1748 + * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read
1749 + * SMICS_CLEAR : Write 1 to clear the FIFOs.
1750 + * SMICS_START : Write 1 to start the programmed transfer.
1751 + * SMICS_ACTIVE        : Reads as 1 when a programmed transfer is underway.
1752 + * SMICS_DONE  : Reads as 1 when transfer finished. For RX, not set until
1753 + *               FIFO emptied.
1754 + * SMICS_ENABLE        : Set to 1 to enable the SMI peripheral, 0 to disable.
1755 + */
1756 +
1757 +#define SMICS_RXF      (1 << 31)
1758 +#define SMICS_TXE      (1 << 30)
1759 +#define SMICS_RXD      (1 << 29)
1760 +#define SMICS_TXD      (1 << 28)
1761 +#define SMICS_RXR      (1 << 27)
1762 +#define SMICS_TXW      (1 << 26)
1763 +#define SMICS_AFERR    (1 << 25)
1764 +#define SMICS_EDREQ    (1 << 15)
1765 +#define SMICS_PXLDAT   (1 << 14)
1766 +#define SMICS_SETERR   (1 << 13)
1767 +#define SMICS_PVMODE   (1 << 12)
1768 +#define SMICS_INTR     (1 << 11)
1769 +#define SMICS_INTT     (1 << 10)
1770 +#define SMICS_INTD     (1 << 9)
1771 +#define SMICS_TEEN     (1 << 8)
1772 +#define SMICS_PAD1     (1 << 7)
1773 +#define SMICS_PAD0     (1 << 6)
1774 +#define SMICS_WRITE    (1 << 5)
1775 +#define SMICS_CLEAR    (1 << 4)
1776 +#define SMICS_START    (1 << 3)
1777 +#define SMICS_ACTIVE   (1 << 2)
1778 +#define SMICS_DONE     (1 << 1)
1779 +#define SMICS_ENABLE   (1 << 0)
1780 +
1781 +/* Address register bits: */
1782 +
1783 +#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
1784 +#define SMIA_DEVICE_OFFS (8)
1785 +#define SMIA_ADDR_MASK (0x3f)  /* bits 5 -> 0 */
1786 +#define SMIA_ADDR_OFFS (0)
1787 +
1788 +/* DMA control register bits:
1789 + * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued.
1790 + * SMIDC_DMAP  : DMA passthrough: when set to 0, top two data pins are used by
1791 + *               SMI as usual. When set to 1, the top two pins are used for
1792 + *               external DREQs: pin 16 read request, 17 write.
1793 + * SMIDC_PANIC*        : Threshold at which DMA will panic during read/write.
1794 + * SMIDC_REQ*  : Threshold at which DMA will generate a DREQ.
1795 + */
1796 +
1797 +#define SMIDC_DMAEN            (1 << 28)
1798 +#define SMIDC_DMAP             (1 << 24)
1799 +#define SMIDC_PANICR_MASK      (0x3f << 18)
1800 +#define SMIDC_PANICR_OFFS      (18)
1801 +#define SMIDC_PANICW_MASK      (0x3f << 12)
1802 +#define SMIDC_PANICW_OFFS      (12)
1803 +#define SMIDC_REQR_MASK                (0x3f << 6)
1804 +#define SMIDC_REQR_OFFS                (6)
1805 +#define SMIDC_REQW_MASK                (0x3f)
1806 +#define SMIDC_REQW_OFFS                (0)
1807 +
1808 +/* Device settings register bits: same for all 4 (or 3?) device register sets.
1809 + * Device read settings:
1810 + * SMIDSR_RWIDTH       : Read transfer width. 00 = 8bit, 01 = 16bit,
1811 + *                       10 = 18bit, 11 = 9bit.
1812 + * SMIDSR_RSETUP       : Read setup time: number of core cycles between chip
1813 + *                       select/address and read strobe. Min 1, max 64.
1814 + * SMIDSR_MODE68       : 1 for System 68 mode (i.e. enable + direction pins,
1815 + *                       rather than OE + WE pin)
1816 + * SMIDSR_FSETUP       : If set to 1, setup time only applies to first
1817 + *                       transfer after address change.
1818 + * SMIDSR_RHOLD                : Number of core cycles between read strobe going
1819 + *                       inactive and CS/address going inactive. Min 1, max 64
1820 + * SMIDSR_RPACEALL     : When set to 1, this device's RPACE value will always
1821 + *                       be used for the next transaction, even if it is not
1822 + *                       to this device.
1823 + * SMIDSR_RPACE                : Number of core cycles spent waiting between CS
1824 + *                       deassert and start of next transfer. Min 1, max 128
1825 + * SMIDSR_RDREQ                : 1 = use external DMA request on SD16 to pace reads
1826 + *                       from device. Must also set DMAP in SMICS.
1827 + * SMIDSR_RSTROBE      : Number of cycles to assert the read strobe.
1828 + *                       min 1, max 128.
1829 + */
1830 +#define SMIDSR_RWIDTH_MASK     ((1<<31)|(1<<30))
1831 +#define SMIDSR_RWIDTH_OFFS     (30)
1832 +#define SMIDSR_RSETUP_MASK     (0x3f << 24)
1833 +#define SMIDSR_RSETUP_OFFS     (24)
1834 +#define SMIDSR_MODE68          (1 << 23)
1835 +#define SMIDSR_FSETUP          (1 << 22)
1836 +#define SMIDSR_RHOLD_MASK      (0x3f << 16)
1837 +#define SMIDSR_RHOLD_OFFS      (16)
1838 +#define SMIDSR_RPACEALL                (1 << 15)
1839 +#define SMIDSR_RPACE_MASK      (0x7f << 8)
1840 +#define SMIDSR_RPACE_OFFS      (8)
1841 +#define SMIDSR_RDREQ           (1 << 7)
1842 +#define SMIDSR_RSTROBE_MASK    (0x7f)
1843 +#define SMIDSR_RSTROBE_OFFS    (0)
1844 +
1845 +/* Device write settings:
1846 + * SMIDSW_WWIDTH       : Write transfer width. 00 = 8bit, 01 = 16bit,
1847 + *                       10= 18bit, 11 = 9bit.
1848 + * SMIDSW_WSETUP       : Number of cycles between CS assert and write strobe.
1849 + *                       Min 1, max 64.
1850 + * SMIDSW_WFORMAT      : Pixel format of input. 0 = 16bit RGB 565,
1851 + *                       1 = 32bit RGBA 8888
1852 + * SMIDSW_WSWAP                : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
1853 + * SMIDSW_WHOLD                : Time between WE deassert and CS deassert. 1 to 64
1854 + * SMIDSW_WPACEALL     : 1: this device's WPACE will be used for the next
1855 + *                       transfer, regardless of that transfer's device.
1856 + * SMIDSW_WPACE                : Cycles between CS deassert and next CS assert.
1857 + *                       Min 1, max 128
1858 + * SMIDSW_WDREQ                : Use external DREQ on pin 17 to pace writes. DMAP must
1859 + *                       be set in SMICS.
1860 + * SMIDSW_WSTROBE      : Number of cycles to assert the write strobe.
1861 + *                       Min 1, max 128
1862 + */
1863 +#define SMIDSW_WWIDTH_MASK      ((1<<31)|(1<<30))
1864 +#define SMIDSW_WWIDTH_OFFS     (30)
1865 +#define SMIDSW_WSETUP_MASK     (0x3f << 24)
1866 +#define SMIDSW_WSETUP_OFFS     (24)
1867 +#define SMIDSW_WFORMAT         (1 << 23)
1868 +#define SMIDSW_WSWAP           (1 << 22)
1869 +#define SMIDSW_WHOLD_MASK      (0x3f << 16)
1870 +#define SMIDSW_WHOLD_OFFS      (16)
1871 +#define SMIDSW_WPACEALL                (1 << 15)
1872 +#define SMIDSW_WPACE_MASK      (0x7f << 8)
1873 +#define SMIDSW_WPACE_OFFS      (8)
1874 +#define SMIDSW_WDREQ           (1 << 7)
1875 +#define SMIDSW_WSTROBE_MASK     (0x7f)
1876 +#define SMIDSW_WSTROBE_OFFS     (0)
1877 +
1878 +/* Direct transfer control + status register
1879 + * SMIDCS_WRITE        : Direction of transfer: 1 -> write, 0 -> read
1880 + * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear.
1881 + * SMIDCS_START        : Write 1 to start a transfer, if one is not already underway.
1882 + * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
1883 + */
1884 +
1885 +#define SMIDCS_WRITE           (1 << 3)
1886 +#define SMIDCS_DONE            (1 << 2)
1887 +#define SMIDCS_START           (1 << 1)
1888 +#define SMIDCS_ENABLE          (1 << 0)
1889 +
1890 +/* Direct transfer address register
1891 + * SMIDA_DEVICE        : Indicates which of the device settings banks should be used.
1892 + * SMIDA_ADDR  : The value to be asserted on the address pins.
1893 + */
1894 +
1895 +#define SMIDA_DEVICE_MASK      ((1<<9)|(1<<8))
1896 +#define SMIDA_DEVICE_OFFS      (8)
1897 +#define SMIDA_ADDR_MASK                (0x3f)
1898 +#define SMIDA_ADDR_OFFS                (0)
1899 +
1900 +/* FIFO debug register
1901 + * SMIFD_FLVL  : The high-tide mark of FIFO count during the most recent txfer
1902 + * SMIFD_FCNT  : The current FIFO count.
1903 + */
1904 +#define SMIFD_FLVL_MASK                (0x3f << 8)
1905 +#define SMIFD_FLVL_OFFS                (8)
1906 +#define SMIFD_FCNT_MASK                (0x3f)
1907 +#define SMIFD_FCNT_OFFS                (0)
1908 +
1909 +#endif /* BCM2835_SMI_IMPLEMENTATION */
1910 +
1911 +#endif /* BCM2835_SMI_H */