1 --- a/arch/mips/pci/Makefile
2 +++ b/arch/mips/pci/Makefile
3 @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
4 obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
6 obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
7 +obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
8 obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
9 obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
10 obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
12 +++ b/arch/mips/pci/pci-ar2315.c
15 + * This program is free software; you can redistribute it and/or
16 + * modify it under the terms of the GNU General Public License
17 + * as published by the Free Software Foundation; either version 2
18 + * of the License, or (at your option) any later version.
20 + * This program is distributed in the hope that it will be useful,
21 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 + * GNU General Public License for more details.
25 + * You should have received a copy of the GNU General Public License
26 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
30 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
31 + * and interrupt. PCI interface supports MMIO access method, but does not
32 + * seem to support I/O ports.
34 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
35 + * a memory read/write command on the PCI bus. 30 LSBs of address on
36 + * the bus are taken from memory read/write request and 2 MSBs are
37 + * determined by PCI unit configuration.
39 + * To work with the configuration space instead of memory is necessary set
40 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
42 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
43 + * controller BARs are programmend as if an external device is programmed.
44 + * Which means that during configuration, IDSEL pin of the chip should be
47 + * We know (and support) only one board that uses the PCI interface -
48 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
49 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
50 + * and IDSEL pin of AR125 is connected to AD[16] line.
53 +#include <linux/types.h>
54 +#include <linux/pci.h>
55 +#include <linux/platform_device.h>
56 +#include <linux/kernel.h>
57 +#include <linux/init.h>
58 +#include <linux/mm.h>
59 +#include <linux/delay.h>
60 +#include <linux/irq.h>
61 +#include <linux/io.h>
62 +#include <asm/paccess.h>
63 +#include <ath25_platform.h>
65 +#include <ar2315_regs.h>
68 + * PCI Bus Interface Registers
70 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
72 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
74 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
76 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
77 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
78 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
79 +#define AR2315_PCIMISC_RST_MODE 0x00000030
80 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
81 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
82 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
83 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
84 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
85 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
86 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
87 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
90 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
92 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
94 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
96 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
97 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
98 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
99 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
101 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
103 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
104 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
105 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
106 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
108 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
110 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
112 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
114 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
116 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
118 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
120 +/* PCI interrupt status (write one to clear) */
121 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500)
123 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
124 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
125 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
126 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
127 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
128 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
129 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
130 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
131 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
132 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
133 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
134 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
136 +/* PCI interrupt mask */
137 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504)
139 +/* Global PCI interrupt enable */
140 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508)
142 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
143 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
145 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
146 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
147 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
148 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
149 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
150 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
153 + * PCI interrupts, which share IP5
154 + * Keep ordered according to AR2315_PCI_INT_XXX bits
156 +#define AR2315_PCI_IRQ_BASE 0x50
157 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
158 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
159 +#define AR2315_PCI_IRQ_COUNT 2
160 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
162 +/* Arbitrary size of memory region to access the configuration space */
163 +#define AR2315_PCI_CFG_SIZE 0x00100000
165 +#define AR2315_PCI_HOST_SLOT 3
166 +#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
168 +/* ??? access BAR */
169 +#define AR2315_PCI_HOST_MBAR0 0x10000000
170 +/* RAM access BAR */
171 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
172 +/* ??? access BAR */
173 +#define AR2315_PCI_HOST_MBAR2 0x30000000
175 +struct ar2315_pci_ctrl {
176 + void __iomem *cfg_mem;
177 + struct pci_controller pci_ctrl;
178 + struct resource mem_res;
179 + struct resource io_res;
182 +static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
184 + struct pci_controller *hose = bus->sysdata;
186 + return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
189 +static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
190 + int where, int size, u32 *ptr, bool write)
192 + int func = PCI_FUNC(devfn);
193 + int dev = PCI_SLOT(devfn);
194 + u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
195 + u32 mask = 0xffffffff >> 8 * (4 - size);
196 + u32 sh = (where & 3) * 8;
199 + /* Prevent access past the remapped area */
200 + if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
201 + return PCIBIOS_DEVICE_NOT_FOUND;
203 + /* Clear pending errors */
204 + ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
205 + /* Select Configuration access */
206 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
208 + mb(); /* PCI must see space change before we begin */
210 + value = __raw_readl(apc->cfg_mem + addr);
212 + isr = ar231x_read_reg(AR2315_PCI_ISR);
213 + if (isr & AR2315_PCI_INT_ABORT)
217 + value = (value & ~(mask << sh)) | *ptr << sh;
218 + __raw_writel(value, apc->cfg_mem + addr);
219 + isr = ar231x_read_reg(AR2315_PCI_ISR);
220 + if (isr & AR2315_PCI_INT_ABORT)
223 + *ptr = (value >> sh) & mask;
229 + ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
234 + /* Select Memory access */
235 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
237 + return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
238 + PCIBIOS_SUCCESSFUL;
241 +static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
242 + unsigned devfn, int where, u32 *val)
244 + return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
248 +static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
249 + unsigned devfn, int where, u32 val)
251 + return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
255 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
256 + int size, u32 *value)
258 + struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
260 + if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
261 + return PCIBIOS_DEVICE_NOT_FOUND;
263 + return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
266 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
267 + int size, u32 value)
269 + struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
271 + if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
272 + return PCIBIOS_DEVICE_NOT_FOUND;
274 + return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
277 +static struct pci_ops ar2315_pci_ops = {
278 + .read = ar2315_pci_cfg_read,
279 + .write = ar2315_pci_cfg_write,
282 +static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
284 + unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
288 + res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
289 + if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
292 + /* Program MBARs */
293 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
294 + AR2315_PCI_HOST_MBAR0);
295 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
296 + AR2315_PCI_HOST_MBAR1);
297 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
298 + AR2315_PCI_HOST_MBAR2);
301 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
302 + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
303 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
304 + PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
309 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
311 + u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
312 + ar231x_read_reg(AR2315_PCI_IMR);
314 + if (pending & AR2315_PCI_INT_EXT)
315 + generic_handle_irq(AR2315_PCI_IRQ_EXT);
316 + else if (pending & AR2315_PCI_INT_ABORT)
317 + generic_handle_irq(AR2315_PCI_IRQ_ABORT);
319 + spurious_interrupt();
322 +static void ar2315_pci_irq_mask(struct irq_data *d)
324 + u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
326 + ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
329 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
331 + u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
333 + ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
334 + ar231x_write_reg(AR2315_PCI_ISR, m);
337 +static void ar2315_pci_irq_unmask(struct irq_data *d)
339 + u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
341 + ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
344 +static struct irq_chip ar2315_pci_irq_chip = {
345 + .name = "AR2315-PCI",
346 + .irq_mask = ar2315_pci_irq_mask,
347 + .irq_mask_ack = ar2315_pci_irq_mask_ack,
348 + .irq_unmask = ar2315_pci_irq_unmask,
351 +static void ar2315_pci_irq_init(void)
355 + ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
356 + ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
357 + AR2315_PCI_INT_EXT), 0);
359 + for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
360 + int irq = AR2315_PCI_IRQ_BASE + i;
362 + irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
366 + irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
368 + /* Clear any pending Abort or external Interrupts
369 + * and enable interrupt processing */
370 + ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
371 + AR2315_PCI_INT_EXT));
372 + ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
375 +static int ar2315_pci_probe(struct platform_device *pdev)
377 + struct ar2315_pci_ctrl *apc;
378 + struct device *dev = &pdev->dev;
381 + apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
385 + apc->mem_res.name = "AR2315 PCI mem space";
386 + apc->mem_res.start = AR2315_PCIEXT;
387 + apc->mem_res.end = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1;
388 + apc->mem_res.flags = IORESOURCE_MEM;
390 + /* Remap PCI config space */
391 + apc->cfg_mem = devm_ioremap_nocache(dev, AR2315_PCIEXT,
392 + AR2315_PCI_CFG_SIZE);
393 + if (!apc->cfg_mem) {
394 + dev_err(dev, "failed to remap PCI config space\n");
398 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
399 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
400 + AR2315_PCIRST_LOW);
403 + /* Bring the PCI out of reset */
404 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
405 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
407 + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
408 + 0x1E | /* 1GB uncached */
409 + (1 << 5) | /* Enable uncached */
410 + (0x2 << 30) /* Base: 0x80000000 */);
411 + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
415 + err = ar2315_pci_host_setup(apc);
419 + ar2315_pci_irq_init();
421 + /* PCI controller does not support I/O ports */
422 + apc->io_res.name = "AR2315 IO space";
423 + apc->io_res.start = 0;
424 + apc->io_res.end = 0;
425 + apc->io_res.flags = IORESOURCE_IO,
427 + apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
428 + apc->pci_ctrl.mem_resource = &apc->mem_res,
429 + apc->pci_ctrl.io_resource = &apc->io_res,
431 + register_pci_controller(&apc->pci_ctrl);
436 +static struct platform_driver ar2315_pci_driver = {
437 + .probe = ar2315_pci_probe,
439 + .name = "ar2315-pci",
440 + .owner = THIS_MODULE,
444 +static int __init ar2315_pci_init(void)
446 + return platform_driver_register(&ar2315_pci_driver);
448 +arch_initcall(ar2315_pci_init);
450 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
452 + return AR2315_PCI_IRQ_EXT;
455 +int pcibios_plat_dev_init(struct pci_dev *dev)
459 --- a/arch/mips/ath25/Kconfig
460 +++ b/arch/mips/ath25/Kconfig
461 @@ -9,3 +9,10 @@ config SOC_AR2315
467 + bool "AR2315 PCI controller support"
468 + depends on SOC_AR2315
472 --- a/arch/mips/ath25/ar2315.c
473 +++ b/arch/mips/ath25/ar2315.c
474 @@ -116,6 +116,10 @@ static void ar2315_irq_dispatch(void)
475 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
476 else if (pending & CAUSEF_IP4)
477 do_IRQ(AR2315_IRQ_ENET0_INTRS);
478 +#ifdef CONFIG_PCI_AR2315
479 + else if (pending & CAUSEF_IP5)
480 + do_IRQ(AR2315_IRQ_LCBUS_PCI);
482 else if (pending & CAUSEF_IP2)
483 do_IRQ(AR2315_IRQ_MISC_INTRS);
484 else if (pending & CAUSEF_IP7)
485 @@ -427,4 +431,31 @@ void __init ar2315_arch_init(void)
487 ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
488 ar2315_apb_frequency());
490 +#ifdef CONFIG_PCI_AR2315
491 + if (ath25_soc == ATH25_SOC_AR2315) {
492 + /* Reset PCI DMA logic */
493 + ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
495 + ar231x_mask_reg(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
498 + /* Configure endians */
499 + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
500 + AR2315_CONFIG_PCIAHB_BRIDGE);
502 + /* Configure as PCI host with DMA */
503 + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
504 + (AR2315_PCICLK_IN_FREQ_DIV_6 <<
505 + AR2315_PCICLK_DIV_S));
506 + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
507 + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
508 + AR2315_IF_MASK, AR2315_IF_PCI |
509 + AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
510 + (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
511 + AR2315_IF_PCI_CLK_SHIFT));
513 + platform_device_register_simple("ar2315-pci", -1, NULL, 0);