1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
8 + bool "Atheros 231x/531x SoC support"
11 + select DMA_NONCOHERENT
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
18 + Support for AR231x and AR531x based boards
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
42 +++ b/arch/mips/ath25/Platform
45 +# Atheros AR531X/AR231X WiSoC
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
51 +++ b/arch/mips/ath25/Kconfig
54 + bool "Atheros 5312/2312+ support"
59 + bool "Atheros 2315+ support"
63 +++ b/arch/mips/ath25/Makefile
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
79 +++ b/arch/mips/ath25/board.c
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
108 +#include <ath25_platform.h>
109 +#include "devices.h"
113 +void (*ar231x_irq_dispatch)(void);
115 +static inline bool check_radio_magic(u8 *addr)
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
121 +static inline bool check_notempty(u8 *addr)
123 + return *(u32 *)addr != 0xffffffff;
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
165 + u8 *rcfg, *begin, *end;
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
172 + begin = bcfg + 0x1000;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
190 +int __init ar231x_find_config(u8 *flash_limit)
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
209 + /* If that fails, try to at least find valid radio data */
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
216 + pr_warn("WARNING: No board configuration data found!\n");
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
243 + rcfg = find_radio_config(flash_limit, bcfg);
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
265 +static void ar231x_halt(void)
267 + local_irq_disable();
272 +void __init plat_mem_setup(void)
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
284 +asmlinkage void plat_irq_dispatch(void)
286 + ar231x_irq_dispatch();
289 +void __init plat_time_init(void)
291 + ar5312_time_init();
292 + ar2315_time_init();
295 +unsigned int __cpuinit get_c0_compare_int(void)
297 + return CP0_LEGACY_COMPARE_IRQ;
300 +void __init arch_init_irq(void)
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
305 + /* Initialize interrupt controllers */
311 +++ b/arch/mips/ath25/prom.c
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
326 + * Prom setup file for ar231x
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
341 +void __init prom_init(void)
343 + ar5312_prom_init();
344 + ar2315_prom_init();
347 +void __init prom_free_prom_memory(void)
351 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
353 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
354 +#define __ASM_MACH_ATH25_PLATFORM_H
356 +#include <linux/etherdevice.h>
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
410 +#define BOARD_CONFIG_BUFSZ 0x1000
413 + * Platform device information for the Wireless MAC
415 +struct ar231x_board_config {
418 + /* board config data */
419 + struct ar231x_boarddata *config;
421 + /* radio calibration data */
426 + * Platform device information for the Ethernet MAC
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
433 + struct ar231x_board_config *config;
437 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
439 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
442 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
444 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
446 + * This file was derived from: include/asm-mips/cpu-features.h
447 + * Copyright (C) 2003, 2004 Ralf Baechle
448 + * Copyright (C) 2004 Maciej W. Rozycki
450 + * This program is free software; you can redistribute it and/or modify it
451 + * under the terms of the GNU General Public License version 2 as published
452 + * by the Free Software Foundation.
455 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
456 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
459 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
461 +#define cpu_has_tlb 1
462 +#define cpu_has_4kex 1
463 +#define cpu_has_3k_cache 0
464 +#define cpu_has_4k_cache 1
465 +#define cpu_has_tx39_cache 0
466 +#define cpu_has_sb1_cache 0
467 +#define cpu_has_fpu 0
468 +#define cpu_has_32fpr 0
469 +#define cpu_has_counter 1
470 +/* #define cpu_has_watch ? */
471 +/* #define cpu_has_divec ? */
472 +/* #define cpu_has_vce ? */
473 +/* #define cpu_has_cache_cdex_p ? */
474 +/* #define cpu_has_cache_cdex_s ? */
475 +/* #define cpu_has_prefetch ? */
476 +/* #define cpu_has_mcheck ? */
477 +#define cpu_has_ejtag 1
479 +#if !defined(CONFIG_SOC_AR5312)
480 +# define cpu_has_llsc 1
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
486 +# define cpu_has_llsc 0
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
494 +/* #define cpu_has_vtag_icache ? */
495 +/* #define cpu_has_dc_aliases ? */
496 +/* #define cpu_has_ic_fills_f_dc ? */
497 +/* #define cpu_has_pindexed_dcache ? */
499 +/* #define cpu_icache_snoops_remote_store ? */
501 +#define cpu_has_mips32r1 1
503 +#if !defined(CONFIG_SOC_AR5312)
504 +# define cpu_has_mips32r2 1
507 +#define cpu_has_mips64r1 0
508 +#define cpu_has_mips64r2 0
510 +#define cpu_has_dsp 0
511 +#define cpu_has_mipsmt 0
513 +/* #define cpu_has_nofpuex ? */
514 +#define cpu_has_64bits 0
515 +#define cpu_has_64bit_zero_reg 0
516 +#define cpu_has_64bit_gp_regs 0
517 +#define cpu_has_64bit_addresses 0
519 +/* #define cpu_has_inclusive_pcaches ? */
521 +/* #define cpu_dcache_line_size() ? */
522 +/* #define cpu_icache_line_size() ? */
524 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
526 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
529 + * This file is subject to the terms and conditions of the GNU General Public
530 + * License. See the file "COPYING" in the main directory of this archive
531 + * for more details.
533 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
534 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
537 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
538 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
540 +#include <linux/device.h>
541 +#include <ar2315_regs.h>
543 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
546 + extern struct bus_type pci_bus_type;
548 + if (dev && dev->bus == &pci_bus_type)
549 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
554 +static inline dma_addr_t
555 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
557 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
560 +static inline dma_addr_t
561 +plat_map_dma_mem_page(struct device *dev, struct page *page)
563 + return page_to_phys(page) + ar231x_dev_offset(dev);
566 +static inline unsigned long
567 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
569 + return dma_addr - ar231x_dev_offset(dev);
573 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
574 + enum dma_data_direction direction)
578 +static inline int plat_dma_supported(struct device *dev, u64 mask)
583 +static inline void plat_extra_sync_for_device(struct device *dev)
587 +static inline int plat_dma_mapping_error(struct device *dev,
588 + dma_addr_t dma_addr)
593 +static inline int plat_device_is_coherent(struct device *dev)
595 +#ifdef CONFIG_DMA_COHERENT
598 +#ifdef CONFIG_DMA_NONCOHERENT
603 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
605 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
607 +#ifndef __ASM_MACH_ATH25_GPIO_H
608 +#define __ASM_MACH_ATH25_GPIO_H
610 +#include <asm-generic/gpio.h>
612 +#define gpio_get_value __gpio_get_value
613 +#define gpio_set_value __gpio_set_value
614 +#define gpio_cansleep __gpio_cansleep
615 +#define gpio_to_irq __gpio_to_irq
617 +static inline int irq_to_gpio(unsigned irq)
622 +#endif /* __ASM_MACH_ATH25_GPIO_H */
624 +++ b/arch/mips/include/asm/mach-ath25/war.h
627 + * This file is subject to the terms and conditions of the GNU General Public
628 + * License. See the file "COPYING" in the main directory of this archive
629 + * for more details.
631 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
633 +#ifndef __ASM_MACH_ATH25_WAR_H
634 +#define __ASM_MACH_ATH25_WAR_H
636 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
637 +#define R4600_V1_HIT_CACHEOP_WAR 0
638 +#define R4600_V2_HIT_CACHEOP_WAR 0
639 +#define R5432_CP0_INTERRUPT_WAR 0
640 +#define BCM1250_M3_WAR 0
641 +#define SIBYTE_1956_WAR 0
642 +#define MIPS4K_ICACHE_REFILL_WAR 0
643 +#define MIPS_CACHE_SYNC_WAR 0
644 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
645 +#define RM9000_CDEX_SMP_WAR 0
646 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
647 +#define R10000_LLSC_WAR 0
648 +#define MIPS34K_MISSED_ITLB_WAR 0
650 +#endif /* __ASM_MACH_ATH25_WAR_H */
652 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
655 + * Register definitions for AR2315+
657 + * This file is subject to the terms and conditions of the GNU General Public
658 + * License. See the file "COPYING" in the main directory of this archive
659 + * for more details.
661 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
662 + * Copyright (C) 2006 FON Technology, SL.
663 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
664 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
667 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
668 +#define __ASM_MACH_ATH25_AR2315_REGS_H
673 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
674 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
675 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
676 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
677 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
680 + * Miscellaneous interrupts, which share IP2.
682 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
683 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
684 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
685 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
686 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
687 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
688 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
689 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
690 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
691 +#define AR2315_MISC_IRQ_COUNT 9
694 + * PCI interrupts, which share IP5
695 + * Keep ordered according to AR2315_PCI_INT_XXX bits
697 +#define AR2315_PCI_IRQ_BASE 0x50
698 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
699 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
700 +#define AR2315_PCI_IRQ_COUNT 2
701 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
706 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
707 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
708 +#define AR2315_PCI 0x10100000 /* PCI MMR */
709 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
710 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
711 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
712 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
713 +#define AR2315_UART0 0x11100000 /* UART MMR */
714 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
715 +#define AR2315_PCIEXT 0x80000000 /* pci external */
716 +#define AR2315_PCIEXT_SZ 0x40000000
718 +/* MII registers offset inside Ethernet MMR region */
719 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
722 + * Cold reset register
724 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
726 +#define AR2315_RESET_COLD_AHB 0x00000001
727 +#define AR2315_RESET_COLD_APB 0x00000002
728 +#define AR2315_RESET_COLD_CPU 0x00000004
729 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
730 +#define AR2315_RESET_SYSTEM \
733 + RESET_COLD_AHB) /* full system */
734 +#define AR2317_RESET_SYSTEM 0x00000010
739 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
741 +/* warm reset WLAN0 MAC */
742 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
743 +/* warm reset WLAN0 BaseBand */
744 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
745 +/* warm reset MPEG-TS */
746 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
747 +/* warm reset PCI ahb/dma */
748 +#define AR2315_RESET_PCIDMA 0x00000008
749 +/* warm reset memory controller */
750 +#define AR2315_RESET_MEMCTL 0x00000010
751 +/* warm reset local bus */
752 +#define AR2315_RESET_LOCAL 0x00000020
753 +/* warm reset I2C bus */
754 +#define AR2315_RESET_I2C_RSVD 0x00000040
755 +/* warm reset SPI interface */
756 +#define AR2315_RESET_SPI 0x00000080
757 +/* warm reset UART0 */
758 +#define AR2315_RESET_UART0 0x00000100
759 +/* warm reset IR interface */
760 +#define AR2315_RESET_IR_RSVD 0x00000200
761 +/* cold reset ENET0 phy */
762 +#define AR2315_RESET_EPHY0 0x00000400
763 +/* cold reset ENET0 mac */
764 +#define AR2315_RESET_ENET0 0x00000800
767 + * AHB master arbitration control
769 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
772 +#define AR2315_ARB_CPU 0x00000001
774 +#define AR2315_ARB_WLAN 0x00000002
776 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
778 +#define AR2315_ARB_LOCAL 0x00000008
780 +#define AR2315_ARB_PCI 0x00000010
782 +#define AR2315_ARB_ETHERNET 0x00000020
783 +/* retry policy, debug only */
784 +#define AR2315_ARB_RETRY 0x00000100
789 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
791 +/* EC - AHB bridge endianess */
792 +#define AR2315_CONFIG_AHB 0x00000001
794 +#define AR2315_CONFIG_WLAN 0x00000002
795 +/* MPEG-TS byteswap */
796 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
798 +#define AR2315_CONFIG_PCI 0x00000008
799 +/* Memory controller endianess */
800 +#define AR2315_CONFIG_MEMCTL 0x00000010
801 +/* Local bus byteswap */
802 +#define AR2315_CONFIG_LOCAL 0x00000020
803 +/* Ethernet byteswap */
804 +#define AR2315_CONFIG_ETHERNET 0x00000040
806 +/* CPU write buffer merge */
807 +#define AR2315_CONFIG_MERGE 0x00000200
808 +/* CPU big endian */
809 +#define AR2315_CONFIG_CPU 0x00000400
810 +#define AR2315_CONFIG_PCIAHB 0x00000800
811 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
813 +#define AR2315_CONFIG_SPI 0x00008000
814 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
815 +#define AR2315_CONFIG_CPU_PCI 0x00020000
816 +#define AR2315_CONFIG_CPU_MMR 0x00040000
817 +#define AR2315_CONFIG_BIG 0x00000400
822 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
824 +#define AR2315_NMI_EN 1
827 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
829 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
831 +#define AR2315_REV_MAJ 0x00f0
832 +#define AR2315_REV_MAJ_S 4
833 +#define AR2315_REV_MIN 0x000f
834 +#define AR2315_REV_MIN_S 0
835 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
840 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
842 +#define AR2315_IF_MASK 0x00000007
843 +#define AR2315_IF_DISABLED 0
844 +#define AR2315_IF_PCI 1
845 +#define AR2315_IF_TS_LOCAL 2
846 +/* only for emulation with separate pins */
847 +#define AR2315_IF_ALL 3
848 +#define AR2315_IF_LOCAL_HOST 0x00000008
849 +#define AR2315_IF_PCI_HOST 0x00000010
850 +#define AR2315_IF_PCI_INTR 0x00000020
851 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
852 +#define AR2315_IF_PCI_CLK_INPUT 0
853 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
854 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
855 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
856 +#define AR2315_IF_PCI_CLK_SHIFT 16
859 + * APB Interrupt control
862 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
863 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
864 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
866 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
867 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
868 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
869 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
870 +#define AR2315_ISR_APB 0x0010 /* APB error */
871 +#define AR2315_ISR_TIMER 0x0020 /* timer */
872 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
873 +#define AR2315_ISR_WD 0x0080 /* watchdog */
874 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
876 +#define AR2315_GISR_MISC 0x0001
877 +#define AR2315_GISR_WLAN0 0x0002
878 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
879 +#define AR2315_GISR_LOCALPCI 0x0008
880 +#define AR2315_GISR_WMACPOLL 0x0010
881 +#define AR2315_GISR_TIMER 0x0020
882 +#define AR2315_GISR_ETHERNET 0x0040
885 + * Interrupt routing from IO to the processor IP bits
886 + * Define our inter mask and level
888 +#define AR2315_INTR_MISCIO SR_IBIT3
889 +#define AR2315_INTR_WLAN0 SR_IBIT4
890 +#define AR2315_INTR_ENET0 SR_IBIT5
891 +#define AR2315_INTR_LOCALPCI SR_IBIT6
892 +#define AR2315_INTR_WMACPOLL SR_IBIT7
893 +#define AR2315_INTR_COMPARE SR_IBIT8
898 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
899 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
900 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
901 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
903 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
904 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
905 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
908 + * CPU Performance Counters
910 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
911 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
913 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
914 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
915 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
916 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
917 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
918 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
919 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
921 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
922 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
923 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
924 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
925 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
926 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
927 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
930 + * AHB Error Reporting.
932 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
933 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
934 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
935 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
936 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
938 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
939 + /* write 1 to clear all bits in ERR0 */
940 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
941 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
943 +#define AR2315_PROCERR_HMAST 0x0000000f
944 +#define AR2315_PROCERR_HMAST_DFLT 0
945 +#define AR2315_PROCERR_HMAST_WMAC 1
946 +#define AR2315_PROCERR_HMAST_ENET 2
947 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
948 +#define AR2315_PROCERR_HMAST_LOCAL 4
949 +#define AR2315_PROCERR_HMAST_CPU 5
950 +#define AR2315_PROCERR_HMAST_PCITGT 6
952 +#define AR2315_PROCERR_HMAST_S 0
953 +#define AR2315_PROCERR_HWRITE 0x00000010
954 +#define AR2315_PROCERR_HSIZE 0x00000060
955 +#define AR2315_PROCERR_HSIZE_S 5
956 +#define AR2315_PROCERR_HTRANS 0x00000180
957 +#define AR2315_PROCERR_HTRANS_S 7
958 +#define AR2315_PROCERR_HBURST 0x00000e00
959 +#define AR2315_PROCERR_HBURST_S 9
964 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
965 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
966 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
967 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
968 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
969 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
970 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
972 +/* PLLc Control fields */
973 +#define PLLC_REF_DIV_M 0x00000003
974 +#define PLLC_REF_DIV_S 0
975 +#define PLLC_FDBACK_DIV_M 0x0000007C
976 +#define PLLC_FDBACK_DIV_S 2
977 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
978 +#define PLLC_ADD_FDBACK_DIV_S 7
979 +#define PLLC_CLKC_DIV_M 0x0001c000
980 +#define PLLC_CLKC_DIV_S 14
981 +#define PLLC_CLKM_DIV_M 0x00700000
982 +#define PLLC_CLKM_DIV_S 20
984 +/* CPU CLK Control fields */
985 +#define CPUCLK_CLK_SEL_M 0x00000003
986 +#define CPUCLK_CLK_SEL_S 0
987 +#define CPUCLK_CLK_DIV_M 0x0000000c
988 +#define CPUCLK_CLK_DIV_S 2
990 +/* AMBA CLK Control fields */
991 +#define AMBACLK_CLK_SEL_M 0x00000003
992 +#define AMBACLK_CLK_SEL_S 0
993 +#define AMBACLK_CLK_DIV_M 0x0000000c
994 +#define AMBACLK_CLK_DIV_S 2
996 +/* GPIO MMR base address */
997 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
999 +#define AR2315_RESET_GPIO 5
1002 + * PCI Clock Control
1004 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1006 +#define AR2315_PCICLK_INPUT_M 0x3
1007 +#define AR2315_PCICLK_INPUT_S 0
1009 +#define AR2315_PCICLK_PLLC_CLKM 0
1010 +#define AR2315_PCICLK_PLLC_CLKM1 1
1011 +#define AR2315_PCICLK_PLLC_CLKC 2
1012 +#define AR2315_PCICLK_REF_CLK 3
1014 +#define AR2315_PCICLK_DIV_M 0xc
1015 +#define AR2315_PCICLK_DIV_S 2
1017 +#define AR2315_PCICLK_IN_FREQ 0
1018 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1019 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1020 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1023 + * Observation Control Register
1025 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1026 +#define OCR_GPIO0_IRIN 0x0040
1027 +#define OCR_GPIO1_IROUT 0x0080
1028 +#define OCR_GPIO3_RXCLR 0x0200
1031 + * General Clock Control
1034 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1035 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1036 +#define MISCCLK_PROCREFCLK 0x00000002
1039 + * SDRAM Controller
1040 + * - No read or write buffers are included.
1042 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1043 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1044 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1046 +#define SDRAM_DATA_WIDTH_M 0x00006000
1047 +#define SDRAM_DATA_WIDTH_S 13
1049 +#define SDRAM_COL_WIDTH_M 0x00001E00
1050 +#define SDRAM_COL_WIDTH_S 9
1052 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1053 +#define SDRAM_ROW_WIDTH_S 5
1055 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1056 +#define SDRAM_BANKADDR_BITS_S 3
1059 + * PCI Bus Interface Registers
1061 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1062 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1064 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1065 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1066 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1067 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1068 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1069 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1070 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1071 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1072 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1073 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1074 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1075 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1076 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1079 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1081 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1083 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1084 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1085 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1086 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1087 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1089 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1090 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1091 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1092 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1093 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1095 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1097 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1098 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1100 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1101 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1103 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1105 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1106 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1107 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1108 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1109 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1110 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1111 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1112 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1113 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1114 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1115 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1116 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1117 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1119 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1121 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1122 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1123 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1125 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1126 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1127 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1128 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1129 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1130 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1133 + * Local Bus Interface Registers
1135 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1136 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1137 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1138 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1139 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1140 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1141 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1142 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1143 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1144 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1145 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1146 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1147 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1148 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1149 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1150 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1151 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1152 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1153 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1154 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1155 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1156 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1157 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1158 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1159 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1160 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1162 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1163 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1165 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1166 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1168 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1169 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1170 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1171 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1172 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1173 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1174 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1175 +#define AR2315_LBM_TIMEOUT_SHFT 7
1176 +#define AR2315_LBM_PORTMUX 0x07000000
1178 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1180 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1181 +#define AR2315_LB_TXEN_0 0x01
1182 +#define AR2315_LB_TXEN_1 0x02
1183 +#define AR2315_LB_TXEN_2 0x04
1184 +#define AR2315_LB_TXEN_3 0x08
1186 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1187 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1189 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1190 +#define AR2315_LB_RXEN 0x01
1192 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1193 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1195 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1196 +#define AR2315_INT_TX_DESC 0x0001
1197 +#define AR2315_INT_TX_OK 0x0002
1198 +#define AR2315_INT_TX_ERR 0x0004
1199 +#define AR2315_INT_TX_EOF 0x0008
1200 +#define AR2315_INT_RX_DESC 0x0010
1201 +#define AR2315_INT_RX_OK 0x0020
1202 +#define AR2315_INT_RX_ERR 0x0040
1203 +#define AR2315_INT_RX_EOF 0x0080
1204 +#define AR2315_INT_TX_TRUNC 0x0100
1205 +#define AR2315_INT_TX_STARVE 0x0200
1206 +#define AR2315_INT_LB_TIMEOUT 0x0400
1207 +#define AR2315_INT_LB_ERR 0x0800
1208 +#define AR2315_INT_MBOX_WR 0x1000
1209 +#define AR2315_INT_MBOX_RD 0x2000
1211 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1212 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1214 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1215 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1218 + * IR Interface Registers
1220 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1222 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1224 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1225 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1226 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1227 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1228 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1229 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1230 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1232 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1233 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1234 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1236 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1237 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1238 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1239 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1240 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1241 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1242 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1243 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1244 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1245 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1248 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1249 + * of PCI host controller to enable DMA. The same value should be used as the
1250 + * offset to calculate the physical address of DMA buffer for PCI devices.
1252 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1254 +/* ??? access BAR */
1255 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1256 +/* RAM access BAR */
1257 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1258 +/* ??? access BAR */
1259 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1261 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1263 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1266 + * This file is subject to the terms and conditions of the GNU General Public
1267 + * License. See the file "COPYING" in the main directory of this archive
1268 + * for more details.
1270 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1271 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1272 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1275 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1276 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1278 +#include <asm/addrspace.h>
1283 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1284 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1285 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1286 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1287 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1290 + * Miscellaneous interrupts, which share IP6.
1292 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1293 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1294 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1295 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1296 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1297 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1298 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1299 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1300 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1301 +#define AR5312_MISC_IRQ_COUNT 9
1306 +#define AR5312_WLAN0 0x18000000
1307 +#define AR5312_WLAN1 0x18500000
1308 +#define AR5312_ENET0 0x18100000
1309 +#define AR5312_ENET1 0x18200000
1310 +#define AR5312_SDRAMCTL 0x18300000
1311 +#define AR5312_FLASHCTL 0x18400000
1312 +#define AR5312_APBBASE 0x1c000000
1313 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1314 +#define AR5312_FLASH 0x1e000000
1317 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1318 + * should be considered available. The AR5312 supports 2 enet MACS,
1319 + * even though many reference boards only actually use 1 of them
1320 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1321 + * The AR2312 supports 1 enet MAC.
1323 +#define AR5312_NUM_ENET_MAC 2
1326 + * Need these defines to determine true number of ethernet MACs
1328 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1329 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1330 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1332 +/* MII registers offset inside Ethernet MMR region */
1333 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1334 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1337 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1338 + * should be considered available.
1340 +#define AR5312_NUM_WMAC 2
1342 +/* Reset/Timer Block Address Map */
1343 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1344 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1345 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1346 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1347 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1348 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1349 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1350 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1351 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1352 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1353 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1354 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1355 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1356 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1357 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1359 +/* AR5312_WD_CTRL register bit field definitions */
1360 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1361 +#define AR5312_WD_CTRL_NMI 0x0001
1362 +#define AR5312_WD_CTRL_RESET 0x0002
1364 +/* AR5312_ISR register bit field definitions */
1365 +#define AR5312_ISR_TIMER 0x0001
1366 +#define AR5312_ISR_AHBPROC 0x0002
1367 +#define AR5312_ISR_AHBDMA 0x0004
1368 +#define AR5312_ISR_GPIO 0x0008
1369 +#define AR5312_ISR_UART0 0x0010
1370 +#define AR5312_ISR_UART0DMA 0x0020
1371 +#define AR5312_ISR_WD 0x0040
1372 +#define AR5312_ISR_LOCAL 0x0080
1374 +/* AR5312_RESET register bit field definitions */
1375 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1376 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1377 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1378 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1379 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1380 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1381 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1382 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1383 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1384 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1385 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1386 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1387 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1388 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1389 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1390 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1391 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1392 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1394 +#define AR5312_RESET_WMAC0_BITS \
1395 + (AR5312_RESET_WLAN0 |\
1396 + AR5312_RESET_WARM_WLAN0_MAC |\
1397 + AR5312_RESET_WARM_WLAN0_BB)
1399 +#define AR5312_RESET_WMAC1_BITS \
1400 + (AR5312_RESET_WLAN1 |\
1401 + AR5312_RESET_WARM_WLAN1_MAC |\
1402 + AR5312_RESET_WARM_WLAN1_BB)
1404 +/* AR5312_CLOCKCTL1 register bit field definitions */
1405 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1406 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1407 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1408 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1409 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1411 +/* Valid for AR5312 and AR2312 */
1412 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1413 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1414 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1415 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1416 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1418 +/* Valid for AR2313 */
1419 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1420 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1421 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1422 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1423 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1425 +/* AR5312_ENABLE register bit field definitions */
1426 +#define AR5312_ENABLE_WLAN0 0x0001
1427 +#define AR5312_ENABLE_ENET0 0x0002
1428 +#define AR5312_ENABLE_ENET1 0x0004
1429 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1430 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1431 +#define AR5312_ENABLE_WLAN1 \
1432 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1433 + AR5312_ENABLE_WLAN1_DMA)
1435 +/* AR5312_REV register bit field definitions */
1436 +#define AR5312_REV_WMAC_MAJ 0xf000
1437 +#define AR5312_REV_WMAC_MAJ_S 12
1438 +#define AR5312_REV_WMAC_MIN 0x0f00
1439 +#define AR5312_REV_WMAC_MIN_S 8
1440 +#define AR5312_REV_MAJ 0x00f0
1441 +#define AR5312_REV_MAJ_S 4
1442 +#define AR5312_REV_MIN 0x000f
1443 +#define AR5312_REV_MIN_S 0
1444 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1446 +/* Major revision numbers, bits 7..4 of Revision ID register */
1447 +#define AR5312_REV_MAJ_AR5312 0x4
1448 +#define AR5312_REV_MAJ_AR2313 0x5
1450 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1451 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1452 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1454 +/* AR5312_FLASHCTL register bit field definitions */
1455 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1456 +#define FLASHCTL_IDCY_S 0
1457 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1458 +#define FLASHCTL_WST1_S 5
1459 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1460 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1461 +#define FLASHCTL_WST2_S 11
1462 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1463 +#define FLASHCTL_AC_S 16
1464 +#define FLASHCTL_AC_128K 0x00000000
1465 +#define FLASHCTL_AC_256K 0x00010000
1466 +#define FLASHCTL_AC_512K 0x00020000
1467 +#define FLASHCTL_AC_1M 0x00030000
1468 +#define FLASHCTL_AC_2M 0x00040000
1469 +#define FLASHCTL_AC_4M 0x00050000
1470 +#define FLASHCTL_AC_8M 0x00060000
1471 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1472 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1473 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1474 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1475 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1476 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1477 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1478 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1479 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1480 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1481 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1482 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1483 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1485 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1486 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1487 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1488 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1490 +/* ARM SDRAM Controller -- just enough to determine memory size */
1491 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1492 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1493 +#define MEM_CFG1_AC0_S 8
1494 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1495 +#define MEM_CFG1_AC1_S 12
1497 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1499 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1501 +++ b/arch/mips/ath25/ar5312.c
1504 + * This file is subject to the terms and conditions of the GNU General Public
1505 + * License. See the file "COPYING" in the main directory of this archive
1506 + * for more details.
1508 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1509 + * Copyright (C) 2006 FON Technology, SL.
1510 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1511 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1512 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1516 + * Platform devices for Atheros SoCs
1519 +#include <generated/autoconf.h>
1520 +#include <linux/init.h>
1521 +#include <linux/module.h>
1522 +#include <linux/types.h>
1523 +#include <linux/string.h>
1524 +#include <linux/mtd/physmap.h>
1525 +#include <linux/platform_device.h>
1526 +#include <linux/kernel.h>
1527 +#include <linux/reboot.h>
1528 +#include <linux/leds.h>
1529 +#include <linux/gpio.h>
1530 +#include <asm/bootinfo.h>
1531 +#include <asm/reboot.h>
1532 +#include <asm/time.h>
1533 +#include <linux/irq.h>
1534 +#include <linux/io.h>
1536 +#include <ath25_platform.h>
1537 +#include <ar5312_regs.h>
1538 +#include <ar231x.h>
1539 +#include "devices.h"
1540 +#include "ar5312.h"
1542 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1544 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1545 + ar231x_read_reg(AR5312_IMR);
1547 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1548 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1549 + (void)ar231x_read_reg(AR5312_TIMER);
1550 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1551 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1552 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1553 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1554 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1555 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1557 + spurious_interrupt();
1560 +static asmlinkage void
1561 +ar5312_irq_dispatch(void)
1563 + int pending = read_c0_status() & read_c0_cause();
1565 + if (pending & CAUSEF_IP2)
1566 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1567 + else if (pending & CAUSEF_IP3)
1568 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1569 + else if (pending & CAUSEF_IP4)
1570 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1571 + else if (pending & CAUSEF_IP5)
1572 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1573 + else if (pending & CAUSEF_IP6)
1574 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1575 + else if (pending & CAUSEF_IP7)
1576 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1578 + spurious_interrupt();
1581 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1583 +ar5312_misc_irq_unmask(struct irq_data *d)
1587 + imr = ar231x_read_reg(AR5312_IMR);
1588 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1589 + ar231x_write_reg(AR5312_IMR, imr);
1592 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1594 +ar5312_misc_irq_mask(struct irq_data *d)
1598 + imr = ar231x_read_reg(AR5312_IMR);
1599 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1600 + ar231x_write_reg(AR5312_IMR, imr);
1601 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1604 +static struct irq_chip ar5312_misc_irq_chip = {
1605 + .name = "AR5312-MISC",
1606 + .irq_unmask = ar5312_misc_irq_unmask,
1607 + .irq_mask = ar5312_misc_irq_mask,
1610 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1612 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1613 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1614 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1615 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1617 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1618 + proc_addr, proc1, dma_addr, dma1);
1620 + machine_restart("AHB error"); /* Catastrophic failure */
1621 + return IRQ_HANDLED;
1624 +static struct irqaction ar5312_ahb_proc_interrupt = {
1625 + .handler = ar5312_ahb_proc_handler,
1626 + .name = "ar5312_ahb_proc_interrupt",
1629 +void __init ar5312_irq_init(void)
1636 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1637 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1638 + int irq = AR231X_MISC_IRQ_BASE + i;
1640 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1641 + handle_level_irq);
1643 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1644 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1647 +static void ar5312_device_reset_set(u32 mask)
1651 + val = ar231x_read_reg(AR5312_RESET);
1652 + ar231x_write_reg(AR5312_RESET, val | mask);
1655 +static void ar5312_device_reset_clear(u32 mask)
1659 + val = ar231x_read_reg(AR5312_RESET);
1660 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1663 +static struct physmap_flash_data ar5312_flash_data = {
1667 +static struct resource ar5312_flash_resource = {
1668 + .start = AR5312_FLASH,
1669 + .end = AR5312_FLASH + 0x800000 - 1,
1670 + .flags = IORESOURCE_MEM,
1673 +static struct ar231x_eth ar5312_eth0_data = {
1674 + .reset_set = ar5312_device_reset_set,
1675 + .reset_clear = ar5312_device_reset_clear,
1676 + .reset_mac = AR5312_RESET_ENET0,
1677 + .reset_phy = AR5312_RESET_EPHY0,
1678 + .config = &ar231x_board,
1681 +static struct ar231x_eth ar5312_eth1_data = {
1682 + .reset_set = ar5312_device_reset_set,
1683 + .reset_clear = ar5312_device_reset_clear,
1684 + .reset_mac = AR5312_RESET_ENET1,
1685 + .reset_phy = AR5312_RESET_EPHY1,
1686 + .config = &ar231x_board,
1689 +static struct platform_device ar5312_physmap_flash = {
1690 + .name = "physmap-flash",
1692 + .dev.platform_data = &ar5312_flash_data,
1693 + .resource = &ar5312_flash_resource,
1694 + .num_resources = 1,
1697 +#ifdef CONFIG_LEDS_GPIO
1698 +static struct gpio_led ar5312_leds[] = {
1699 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1702 +static const struct gpio_led_platform_data ar5312_led_data = {
1703 + .num_leds = ARRAY_SIZE(ar5312_leds),
1704 + .leds = (void *)ar5312_leds,
1707 +static struct platform_device ar5312_gpio_leds = {
1708 + .name = "leds-gpio",
1710 + .dev.platform_data = (void *)&ar5312_led_data,
1715 + * NB: This mapping size is larger than the actual flash size,
1716 + * but this shouldn't be a problem here, because the flash
1717 + * will simply be mapped multiple times.
1719 +static char __init *ar5312_flash_limit(void)
1723 + * Configure flash bank 0.
1724 + * Assume 8M window size. Flash will be aliased if it's smaller
1726 + ctl = FLASHCTL_E |
1729 + (0x01 << FLASHCTL_IDCY_S) |
1730 + (0x07 << FLASHCTL_WST1_S) |
1731 + (0x07 << FLASHCTL_WST2_S) |
1732 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1734 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1736 + /* Disable other flash banks */
1737 + ar231x_write_reg(AR5312_FLASHCTL1,
1738 + ar231x_read_reg(AR5312_FLASHCTL1) &
1739 + ~(FLASHCTL_E | FLASHCTL_AC));
1741 + ar231x_write_reg(AR5312_FLASHCTL2,
1742 + ar231x_read_reg(AR5312_FLASHCTL2) &
1743 + ~(FLASHCTL_E | FLASHCTL_AC));
1745 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1748 +int __init ar5312_init_devices(void)
1750 + struct ar231x_boarddata *config;
1757 + /* Locate board/radio config data */
1758 + ar231x_find_config(ar5312_flash_limit());
1759 + config = ar231x_board.config;
1761 + /* AR2313 has CPU minor rev. 10 */
1762 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1763 + ar231x_devtype = DEV_TYPE_AR2313;
1765 + /* AR2312 shares the same Silicon ID as AR5312 */
1766 + else if (config->flags & BD_ISCASPER)
1767 + ar231x_devtype = DEV_TYPE_AR2312;
1769 + /* Everything else is probably AR5312 or compatible */
1771 + ar231x_devtype = DEV_TYPE_AR5312;
1773 + /* fixup flash width */
1774 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1776 + case FLASHCTL_MW16:
1777 + ar5312_flash_data.width = 2;
1779 + case FLASHCTL_MW8:
1781 + ar5312_flash_data.width = 1;
1785 + platform_device_register(&ar5312_physmap_flash);
1787 +#ifdef CONFIG_LEDS_GPIO
1788 + ar5312_leds[0].gpio = config->sys_led_gpio;
1789 + platform_device_register(&ar5312_gpio_leds);
1792 + /* Fix up MAC addresses if necessary */
1793 + if (is_broadcast_ether_addr(config->enet0_mac))
1794 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1796 + /* If ENET0 and ENET1 have the same mac address,
1797 + * increment the one from ENET1 */
1798 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1799 + c = config->enet1_mac + 5;
1800 + while ((c >= config->enet1_mac) && !(++(*c)))
1804 + switch (ar231x_devtype) {
1805 + case DEV_TYPE_AR5312:
1806 + ar5312_eth0_data.macaddr = config->enet0_mac;
1807 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1808 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1809 + &ar5312_eth0_data);
1811 + ar5312_eth1_data.macaddr = config->enet1_mac;
1812 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1813 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1814 + &ar5312_eth1_data);
1816 + if (!ar231x_board.radio)
1819 + if (!(config->flags & BD_WLAN0))
1822 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1825 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1826 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1828 + case DEV_TYPE_AR2312:
1829 + case DEV_TYPE_AR2313:
1830 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1831 + ar5312_eth1_data.macaddr = config->enet0_mac;
1832 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1833 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1834 + &ar5312_eth1_data);
1836 + if (!ar231x_board.radio)
1843 + if (config->flags & BD_WLAN1)
1844 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1849 +static void ar5312_restart(char *command)
1851 + /* reset the system */
1852 + local_irq_disable();
1854 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1858 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1859 + * to determine the predevisor value.
1861 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1864 +ar5312_cpu_frequency(void)
1866 + unsigned int scratch;
1867 + unsigned int predivide_mask, predivide_shift;
1868 + unsigned int multiplier_mask, multiplier_shift;
1869 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1870 + unsigned int doubler_mask;
1873 + /* Trust the bootrom's idea of cpu frequency. */
1874 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1878 + devid = ar231x_read_reg(AR5312_REV);
1879 + devid &= AR5312_REV_MAJ;
1880 + devid >>= AR5312_REV_MAJ_S;
1881 + if (devid == AR5312_REV_MAJ_AR2313) {
1882 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1883 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1884 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1885 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1886 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1887 + } else { /* AR5312 and AR2312 */
1888 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1889 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1890 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1891 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1892 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1896 + * Clocking is derived from a fixed 40MHz input clock.
1898 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1899 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1900 + * flash, Timer, Watchdog Timer)
1902 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1904 + * So, for example, with a PLL multiplier of 5, we have
1906 + * cpu_freq = 200MHz
1907 + * sys_freq = 50MHz
1908 + * cnt_freq = 100MHz
1910 + * We compute the CPU frequency, based on PLL settings.
1913 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1914 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1915 + predivisor = clockctl1_predivide_table[predivide_select];
1916 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1918 + if (clock_ctl1 & doubler_mask)
1919 + multiplier = multiplier << 1;
1921 + return (40000000 / predivisor) * multiplier;
1925 +ar5312_sys_frequency(void)
1927 + return ar5312_cpu_frequency() / 4;
1931 +ar5312_time_init(void)
1936 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1940 +ar5312_prom_init(void)
1942 + u32 memsize, memcfg, bank0AC, bank1AC;
1948 + /* Detect memory size */
1949 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1950 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1951 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1952 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1953 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1955 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1957 + devid = ar231x_read_reg(AR5312_REV);
1958 + devid >>= AR5312_REV_WMAC_MIN_S;
1959 + devid &= AR5312_REV_CHIP;
1960 + ar231x_board.devid = (u16)devid;
1964 +ar5312_plat_setup(void)
1969 + /* Clear any lingering AHB errors */
1970 + ar231x_read_reg(AR5312_PROCADDR);
1971 + ar231x_read_reg(AR5312_DMAADDR);
1972 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1974 + _machine_restart = ar5312_restart;
1975 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1976 + ar5312_sys_frequency());
1980 +++ b/arch/mips/ath25/ar2315.c
1983 + * This file is subject to the terms and conditions of the GNU General Public
1984 + * License. See the file "COPYING" in the main directory of this archive
1985 + * for more details.
1987 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1988 + * Copyright (C) 2006 FON Technology, SL.
1989 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1990 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1991 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1995 + * Platform devices for Atheros SoCs
1998 +#include <generated/autoconf.h>
1999 +#include <linux/init.h>
2000 +#include <linux/module.h>
2001 +#include <linux/types.h>
2002 +#include <linux/string.h>
2003 +#include <linux/platform_device.h>
2004 +#include <linux/kernel.h>
2005 +#include <linux/reboot.h>
2006 +#include <linux/delay.h>
2007 +#include <linux/leds.h>
2008 +#include <linux/gpio.h>
2009 +#include <asm/bootinfo.h>
2010 +#include <asm/reboot.h>
2011 +#include <asm/time.h>
2012 +#include <linux/irq.h>
2013 +#include <linux/io.h>
2015 +#include <ath25_platform.h>
2016 +#include <ar2315_regs.h>
2017 +#include <ar231x.h>
2018 +#include "devices.h"
2019 +#include "ar2315.h"
2021 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2023 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2024 + ar231x_read_reg(AR2315_IMR);
2026 + if (misc_intr & AR2315_ISR_SPI)
2027 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
2028 + else if (misc_intr & AR2315_ISR_TIMER)
2029 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
2030 + else if (misc_intr & AR2315_ISR_AHB)
2031 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
2032 + else if (misc_intr & AR2315_ISR_GPIO) {
2033 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2034 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
2035 + } else if (misc_intr & AR2315_ISR_UART0)
2036 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
2037 + else if (misc_intr & AR2315_ISR_WD) {
2038 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2039 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
2041 + spurious_interrupt();
2045 + * Called when an interrupt is received, this function
2046 + * determines exactly which interrupt it was, and it
2047 + * invokes the appropriate handler.
2049 + * Implicitly, we also define interrupt priority by
2050 + * choosing which to dispatch first.
2052 +static asmlinkage void
2053 +ar2315_irq_dispatch(void)
2055 + int pending = read_c0_status() & read_c0_cause();
2057 + if (pending & CAUSEF_IP3)
2058 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2059 + else if (pending & CAUSEF_IP4)
2060 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2061 + else if (pending & CAUSEF_IP2)
2062 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2063 + else if (pending & CAUSEF_IP7)
2064 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2066 + spurious_interrupt();
2070 +ar2315_misc_irq_unmask(struct irq_data *d)
2074 + imr = ar231x_read_reg(AR2315_IMR);
2075 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
2076 + ar231x_write_reg(AR2315_IMR, imr);
2080 +ar2315_misc_irq_mask(struct irq_data *d)
2084 + imr = ar231x_read_reg(AR2315_IMR);
2085 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
2086 + ar231x_write_reg(AR2315_IMR, imr);
2089 +static struct irq_chip ar2315_misc_irq_chip = {
2090 + .name = "AR2315-MISC",
2091 + .irq_unmask = ar2315_misc_irq_unmask,
2092 + .irq_mask = ar2315_misc_irq_mask,
2095 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2097 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2098 + ar231x_read_reg(AR2315_AHB_ERR1);
2100 + pr_emerg("AHB fatal error\n");
2101 + machine_restart("AHB error"); /* Catastrophic failure */
2103 + return IRQ_HANDLED;
2106 +static struct irqaction ar2315_ahb_proc_interrupt = {
2107 + .handler = ar2315_ahb_proc_handler,
2108 + .name = "ar2315_ahb_proc_interrupt",
2112 +ar2315_irq_init(void)
2119 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2120 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2121 + int irq = AR231X_MISC_IRQ_BASE + i;
2123 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2124 + handle_level_irq);
2126 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2127 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2130 +static void ar2315_device_reset_set(u32 mask)
2134 + val = ar231x_read_reg(AR2315_RESET);
2135 + ar231x_write_reg(AR2315_RESET, val | mask);
2138 +static void ar2315_device_reset_clear(u32 mask)
2142 + val = ar231x_read_reg(AR2315_RESET);
2143 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2146 +static struct ar231x_eth ar2315_eth_data = {
2147 + .reset_set = ar2315_device_reset_set,
2148 + .reset_clear = ar2315_device_reset_clear,
2149 + .reset_mac = AR2315_RESET_ENET0,
2150 + .reset_phy = AR2315_RESET_EPHY0,
2151 + .config = &ar231x_board,
2154 +static struct resource ar2315_spiflash_res[] = {
2156 + .name = "spiflash_read",
2157 + .flags = IORESOURCE_MEM,
2158 + .start = AR2315_SPI_READ,
2159 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2162 + .name = "spiflash_mmr",
2163 + .flags = IORESOURCE_MEM,
2164 + .start = AR2315_SPI_MMR,
2165 + .end = AR2315_SPI_MMR + 12 - 1,
2169 +static struct platform_device ar2315_spiflash = {
2171 + .name = "ar2315-spiflash",
2172 + .resource = ar2315_spiflash_res,
2173 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2176 +static struct resource ar2315_wdt_res[] = {
2178 + .flags = IORESOURCE_MEM,
2179 + .start = AR2315_WD,
2180 + .end = AR2315_WD + 8 - 1,
2183 + .flags = IORESOURCE_IRQ,
2184 + .start = AR2315_MISC_IRQ_WATCHDOG,
2185 + .end = AR2315_MISC_IRQ_WATCHDOG,
2189 +static struct platform_device ar2315_wdt = {
2191 + .name = "ar2315-wdt",
2192 + .resource = ar2315_wdt_res,
2193 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2197 + * NB: We use mapping size that is larger than the actual flash size,
2198 + * but this shouldn't be a problem here, because the flash will simply
2199 + * be mapped multiple times.
2201 +static u8 __init *ar2315_flash_limit(void)
2203 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2206 +#ifdef CONFIG_LEDS_GPIO
2207 +static struct gpio_led ar2315_leds[6];
2208 +static struct gpio_led_platform_data ar2315_led_data = {
2209 + .leds = (void *)ar2315_leds,
2212 +static struct platform_device ar2315_gpio_leds = {
2213 + .name = "leds-gpio",
2216 + .platform_data = (void *)&ar2315_led_data,
2221 +ar2315_init_gpio_leds(void)
2223 + static char led_names[6][6];
2226 + ar2315_led_data.num_leds = 0;
2227 + for (i = 1; i < 8; i++) {
2228 + if ((i == AR2315_RESET_GPIO) ||
2229 + (i == ar231x_board.config->reset_config_gpio))
2232 + if (i == ar231x_board.config->sys_led_gpio)
2233 + strcpy(led_names[led], "wlan");
2235 + sprintf(led_names[led], "gpio%d", i);
2237 + ar2315_leds[led].name = led_names[led];
2238 + ar2315_leds[led].gpio = i;
2239 + ar2315_leds[led].active_low = 0;
2242 + ar2315_led_data.num_leds = led;
2243 + platform_device_register(&ar2315_gpio_leds);
2246 +static inline void ar2315_init_gpio_leds(void)
2252 +ar2315_init_devices(void)
2257 + /* Find board configuration */
2258 + ar231x_find_config(ar2315_flash_limit());
2259 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2261 + ar2315_init_gpio_leds();
2262 + platform_device_register(&ar2315_wdt);
2263 + platform_device_register(&ar2315_spiflash);
2264 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2265 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2266 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2272 +ar2315_restart(char *command)
2274 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2276 + local_irq_disable();
2278 + /* try reset the system via reset control */
2279 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2281 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2282 + * a workaround. Give it some time to attempt a gpio based hardware
2283 + * reset (atheros reference design workaround) */
2284 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2287 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2288 + * workaround. Attempt to jump to the mips reset location -
2289 + * the boot loader itself might be able to recover the system */
2294 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2295 + * to determine the predevisor value.
2297 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2298 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2300 +static unsigned int __init
2301 +ar2315_sys_clk(unsigned int clock_ctl)
2303 + unsigned int pllc_ctrl, cpu_div;
2304 + unsigned int pllc_out, refdiv, fdiv, divby2;
2305 + unsigned int clk_div;
2307 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2308 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2309 + refdiv = clockctl1_predivide_table[refdiv];
2310 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2311 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2313 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2315 + /* clkm input selected */
2316 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2319 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2323 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2327 + pllc_out = 40000000;
2332 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2333 + cpu_div = cpu_div * 2 ?: 1;
2335 + return pllc_out / (clk_div * cpu_div);
2338 +static inline unsigned int
2339 +ar2315_cpu_frequency(void)
2341 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2344 +static inline unsigned int
2345 +ar2315_apb_frequency(void)
2347 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2351 +ar2315_time_init(void)
2356 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2360 +ar2315_prom_init(void)
2362 + u32 memsize, memcfg, devid;
2367 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2368 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2369 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2370 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2372 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2374 + /* Detect the hardware based on the device ID */
2375 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2377 + case 0x91: /* Need to check */
2378 + ar231x_devtype = DEV_TYPE_AR2318;
2381 + ar231x_devtype = DEV_TYPE_AR2317;
2384 + ar231x_devtype = DEV_TYPE_AR2316;
2388 + ar231x_devtype = DEV_TYPE_AR2315;
2391 + ar231x_board.devid = devid;
2395 +ar2315_plat_setup(void)
2402 + /* Clear any lingering AHB errors */
2403 + config = read_c0_config();
2404 + write_c0_config(config & ~0x3);
2405 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2406 + ar231x_read_reg(AR2315_AHB_ERR1);
2407 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2409 + _machine_restart = ar2315_restart;
2410 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2411 + ar2315_apb_frequency());
2414 +++ b/arch/mips/ath25/ar2315.h
2419 +#ifdef CONFIG_SOC_AR2315
2421 +void ar2315_irq_init(void);
2422 +int ar2315_init_devices(void);
2423 +void ar2315_prom_init(void);
2424 +void ar2315_plat_setup(void);
2425 +void ar2315_time_init(void);
2429 +static inline void ar2315_irq_init(void)
2433 +static inline int ar2315_init_devices(void)
2438 +static inline void ar2315_prom_init(void)
2442 +static inline void ar2315_plat_setup(void)
2446 +static inline void ar2315_time_init(void)
2454 +++ b/arch/mips/ath25/ar5312.h
2459 +#ifdef CONFIG_SOC_AR5312
2461 +void ar5312_irq_init(void);
2462 +int ar5312_init_devices(void);
2463 +void ar5312_prom_init(void);
2464 +void ar5312_plat_setup(void);
2465 +void ar5312_time_init(void);
2469 +static inline void ar5312_irq_init(void)
2473 +static inline int ar5312_init_devices(void)
2478 +static inline void ar5312_prom_init(void)
2482 +static inline void ar5312_plat_setup(void)
2486 +static inline void ar5312_time_init(void)
2494 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2496 +#ifndef __ASM_MACH_ATH25_AR231X_H
2497 +#define __ASM_MACH_ATH25_AR231X_H
2499 +#include <linux/types.h>
2500 +#include <linux/io.h>
2502 +#define AR231X_MISC_IRQ_BASE 0x20
2503 +#define AR231X_GPIO_IRQ_BASE 0x30
2505 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2506 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2509 +ar231x_read_reg(u32 reg)
2511 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2515 +ar231x_write_reg(u32 reg, u32 val)
2517 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2521 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2525 + ret = ar231x_read_reg(reg);
2528 + ar231x_write_reg(reg, ret);
2533 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2535 +++ b/arch/mips/ath25/devices.h
2537 +#ifndef __ATH25_DEVICES_H
2538 +#define __ATH25_DEVICES_H
2541 + /* handled by ar5312.c */
2546 + /* handled by ar2315.c */
2555 +extern int ar231x_devtype;
2556 +extern struct ar231x_board_config ar231x_board;
2557 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2559 +int ar231x_find_config(u8 *flash_limit);
2560 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2561 +int ar231x_add_wmac(int nr, u32 base, int irq);
2562 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2563 + int irq, void *pdata);
2565 +static inline bool is_2315(void)
2567 + return (current_cpu_data.cputype == CPU_4KEC);
2570 +static inline bool is_5312(void)
2572 + return !is_2315();
2577 +++ b/arch/mips/ath25/devices.c
2579 +#include <linux/kernel.h>
2580 +#include <linux/init.h>
2581 +#include <linux/serial.h>
2582 +#include <linux/serial_core.h>
2583 +#include <linux/serial_8250.h>
2584 +#include <linux/platform_device.h>
2585 +#include <asm/bootinfo.h>
2587 +#include <ath25_platform.h>
2588 +#include <ar231x.h>
2589 +#include "devices.h"
2590 +#include "ar5312.h"
2591 +#include "ar2315.h"
2593 +struct ar231x_board_config ar231x_board;
2594 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2596 +static struct resource ar231x_eth0_res[] = {
2598 + .name = "eth0_membase",
2599 + .flags = IORESOURCE_MEM,
2602 + .name = "eth0_mii",
2603 + .flags = IORESOURCE_MEM,
2606 + .name = "eth0_irq",
2607 + .flags = IORESOURCE_IRQ,
2611 +static struct resource ar231x_eth1_res[] = {
2613 + .name = "eth1_membase",
2614 + .flags = IORESOURCE_MEM,
2617 + .name = "eth1_mii",
2618 + .flags = IORESOURCE_MEM,
2621 + .name = "eth1_irq",
2622 + .flags = IORESOURCE_IRQ,
2626 +static struct platform_device ar231x_eth[] = {
2629 + .name = "ar231x-eth",
2630 + .resource = ar231x_eth0_res,
2631 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2635 + .name = "ar231x-eth",
2636 + .resource = ar231x_eth1_res,
2637 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2641 +static struct resource ar231x_wmac0_res[] = {
2643 + .name = "wmac0_membase",
2644 + .flags = IORESOURCE_MEM,
2647 + .name = "wmac0_irq",
2648 + .flags = IORESOURCE_IRQ,
2652 +static struct resource ar231x_wmac1_res[] = {
2654 + .name = "wmac1_membase",
2655 + .flags = IORESOURCE_MEM,
2658 + .name = "wmac1_irq",
2659 + .flags = IORESOURCE_IRQ,
2663 +static struct platform_device ar231x_wmac[] = {
2666 + .name = "ar231x-wmac",
2667 + .resource = ar231x_wmac0_res,
2668 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2669 + .dev.platform_data = &ar231x_board,
2673 + .name = "ar231x-wmac",
2674 + .resource = ar231x_wmac1_res,
2675 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2676 + .dev.platform_data = &ar231x_board,
2680 +static const char * const devtype_strings[] = {
2681 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2682 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2683 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2684 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2685 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2686 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2687 + [DEV_TYPE_AR2318] = "Atheros AR2318",
2688 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2691 +const char *get_system_type(void)
2693 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2694 + !devtype_strings[ar231x_devtype])
2695 + return devtype_strings[DEV_TYPE_UNKNOWN];
2696 + return devtype_strings[ar231x_devtype];
2700 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2701 + int irq, void *pdata)
2703 + struct resource *res;
2705 + ar231x_eth[nr].dev.platform_data = pdata;
2706 + res = &ar231x_eth[nr].resource[0];
2707 + res->start = base;
2708 + res->end = base + 0x2000 - 1;
2710 + res->name = mii_name;
2711 + res->start = mii_base;
2712 + res->end = mii_base + 8 - 1;
2716 + return platform_device_register(&ar231x_eth[nr]);
2720 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2722 + struct uart_port s;
2724 + memset(&s, 0, sizeof(s));
2726 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2727 + s.iotype = UPIO_MEM32;
2730 + s.mapbase = mapbase;
2731 + s.uartclk = uartclk;
2733 + early_serial_setup(&s);
2737 +ar231x_add_wmac(int nr, u32 base, int irq)
2739 + struct resource *res;
2741 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2742 + res = &ar231x_wmac[nr].resource[0];
2743 + res->start = base;
2744 + res->end = base + 0x10000 - 1;
2748 + return platform_device_register(&ar231x_wmac[nr]);
2751 +static int __init ar231x_register_devices(void)
2753 + ar5312_init_devices();
2754 + ar2315_init_devices();
2759 +device_initcall(ar231x_register_devices);