4 #include <linux/version.h>
5 #include <asm/cpu-info.h>
6 #include <ar531x_platform.h>
7 #include "ar5312/ar5312.h"
8 #include "ar5315/ar5315.h"
10 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24))
11 extern void (*board_time_init)(void);
15 * C access to CLZ instruction
16 * (count leading zeroes).
18 static inline int clz(unsigned long val)
38 * Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
39 * using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
41 #ifdef CONFIG_ATHEROS_AR5312
42 #define DO_AR5312(...) \
43 if (current_cpu_data.cputype != CPU_4KEC) { \
47 #define DO_AR5312(...)
49 #ifdef CONFIG_ATHEROS_AR5315
50 #define DO_AR5315(...) \
51 if (current_cpu_data.cputype == CPU_4KEC) { \
55 #define DO_AR5315(...)
58 #define AR531X_MISC_IRQ_BASE 0x20
59 #define AR531X_GPIO_IRQ_BASE 0x30
61 /* Software's idea of interrupts handled by "CPU Interrupt Controller" */
62 #define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
63 #define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
65 /* Miscellaneous interrupts, which share IP6 */
66 #define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
67 #define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
68 #define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
69 #define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
70 #define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
71 #define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
72 #define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
73 #define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
74 #define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
75 #define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
76 #define AR531X_MISC_IRQ_COUNT 10
78 /* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
79 #define AR531X_GPIO_IRQ_NONE AR531X_MISC_IRQ_BASE+0
80 #define AR531X_GPIO_IRQ(n) AR531X_MISC_IRQ_BASE+(n)+1
81 #define AR531X_GPIO_IRQ_COUNT 22
83 #define sysRegRead(phys) \
84 (*(volatile u32 *)KSEG1ADDR(phys))
86 #define sysRegWrite(phys, val) \
87 ((*(volatile u32 *)KSEG1ADDR(phys)) = (val))
90 * This is board-specific data that is stored in a "fixed" location in flash.
91 * It is shared across operating systems, so it should not be changed lightly.
92 * The main reason we need it is in order to extract the ethernet MAC
95 struct ar531x_boarddata {
96 u32 magic; /* board data is valid */
97 #define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
98 u16 cksum; /* checksum (starting with BD_REV 2) */
99 u16 rev; /* revision of this struct */
101 char boardName[64]; /* Name of board */
102 u16 major; /* Board major number */
103 u16 minor; /* Board minor number */
104 u32 config; /* Board configuration */
105 #define BD_ENET0 0x00000001 /* ENET0 is stuffed */
106 #define BD_ENET1 0x00000002 /* ENET1 is stuffed */
107 #define BD_UART1 0x00000004 /* UART1 is stuffed */
108 #define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
109 #define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
110 #define BD_SYSLED 0x00000020 /* System LED stuffed */
111 #define BD_EXTUARTCLK 0x00000040 /* External UART clock */
112 #define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
113 #define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
114 #define BD_WLAN0 0x00000200 /* Enable WLAN0 */
115 #define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
116 #define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
117 #define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
118 #define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
119 #define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
120 #define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
121 #define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
122 #define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
123 u16 resetConfigGpio; /* Reset factory GPIO pin */
124 u16 sysLedGpio; /* System LED GPIO pin */
126 u32 cpuFreq; /* CPU core frequency in Hz */
127 u32 sysFreq; /* System frequency in Hz */
128 u32 cntFreq; /* Calculated C0_COUNT frequency */
134 u16 pciId; /* Pseudo PCIID for common code */
135 u16 memCap; /* cap bank1 in MB */
138 u8 wlan1Mac[6]; /* (ar5212) */
141 #define BOARD_CONFIG_BUFSZ 0x1000
143 extern char *board_config, *radio_config;
144 extern void serial_setup(unsigned long mapbase, unsigned int uartclk);
145 extern int ar531x_find_config(char *flash_limit);
147 extern void ar5312_prom_init(void);
148 extern void ar5312_misc_intr_init(int irq_base);
149 extern void ar5312_plat_setup(void);
150 extern asmlinkage void ar5312_irq_dispatch(void);
152 extern void ar5315_prom_init(void);
153 extern void ar5315_misc_intr_init(int irq_base);
154 extern void ar5315_plat_setup(void);
155 extern asmlinkage void ar5315_irq_dispatch(void);
156 extern void ar5315_pci_irq(int irq);
157 static inline u32 sysRegMask(u32 phys, u32 mask, u32 value)
161 reg = sysRegRead(phys);
164 sysRegWrite(phys, reg);
165 reg = sysRegRead(phys); /* flush write to the hardware */