2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/string.h>
20 #include <linux/kernel.h>
21 #include <linux/reboot.h>
22 #include <linux/interrupt.h>
23 #include <asm/bootinfo.h>
24 #include <asm/irq_cpu.h>
26 #include "../ar531x.h"
28 static u32 gpiointmask = 0, gpiointval = 0;
30 static inline void ar5315_gpio_irq(void)
33 sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~AR5315_ISR_GPIO);
35 /* only do one gpio interrupt at a time */
36 pend = (sysRegRead(AR5315_GPIO_DI) ^ gpiointval) & gpiointmask;
40 do_IRQ(AR531X_GPIO_IRQ_BASE + 31 - clz(pend));
45 * Called when an interrupt is received, this function
46 * determines exactly which interrupt it was, and it
47 * invokes the appropriate handler.
49 * Implicitly, we also define interrupt priority by
50 * choosing which to dispatch first.
52 asmlinkage void ar5315_irq_dispatch(void)
54 int pending = read_c0_status() & read_c0_cause();
56 if (pending & CAUSEF_IP3)
57 do_IRQ(AR5315_IRQ_WLAN0_INTRS);
58 else if (pending & CAUSEF_IP4)
59 do_IRQ(AR5315_IRQ_ENET0_INTRS);
60 else if (pending & CAUSEF_IP2) {
61 unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
63 if (ar531x_misc_intrs & AR5315_ISR_SPI)
64 do_IRQ(AR531X_MISC_IRQ_SPI);
65 else if (ar531x_misc_intrs & AR5315_ISR_TIMER)
66 do_IRQ(AR531X_MISC_IRQ_TIMER);
67 else if (ar531x_misc_intrs & AR5315_ISR_AHB)
68 do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
69 else if (ar531x_misc_intrs & AR5315_ISR_GPIO)
71 else if (ar531x_misc_intrs & AR5315_ISR_UART0)
72 do_IRQ(AR531X_MISC_IRQ_UART0);
73 else if (ar531x_misc_intrs & AR5315_ISR_WD)
74 do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
76 do_IRQ(AR531X_MISC_IRQ_NONE);
77 } else if (pending & CAUSEF_IP7)
78 do_IRQ(AR531X_IRQ_CPU_CLOCK);
81 static void ar5315_gpio_intr_enable(unsigned int irq)
84 gpio = irq - AR531X_GPIO_IRQ_BASE;
88 /* reconfigure GPIO line as input */
89 sysRegMask(AR5315_GPIO_CR, AR5315_GPIO_CR_M(gpio), AR5315_GPIO_CR_I(gpio));
91 /* Enable interrupt with edge detection */
92 sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(3));
95 static void ar5315_gpio_intr_disable(unsigned int irq)
98 gpio = irq - AR531X_GPIO_IRQ_BASE;
101 gpiointmask &= ~mask;
103 /* Disable interrupt with edge detection */
104 sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(0));
107 /* Turn on the specified AR531X_MISC_IRQ interrupt */
108 static unsigned int ar5315_gpio_intr_startup(unsigned int irq)
110 ar5315_gpio_intr_enable(irq);
114 /* Turn off the specified AR531X_MISC_IRQ interrupt */
116 ar5315_gpio_intr_shutdown(unsigned int irq)
118 ar5315_gpio_intr_disable(irq);
122 ar5315_gpio_intr_ack(unsigned int irq)
124 ar5315_gpio_intr_disable(irq);
128 ar5315_gpio_intr_end(unsigned int irq)
130 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
131 ar5315_gpio_intr_enable(irq);
134 static struct irq_chip ar5315_gpio_intr_controller = {
135 .typename = "AR5315 GPIO",
136 .startup = ar5315_gpio_intr_startup,
137 .shutdown = ar5315_gpio_intr_shutdown,
138 .enable = ar5315_gpio_intr_enable,
139 .disable = ar5315_gpio_intr_disable,
140 .ack = ar5315_gpio_intr_ack,
141 .end = ar5315_gpio_intr_end,
145 /* Enable the specified AR531X_MISC_IRQ interrupt */
147 ar5315_misc_intr_enable(unsigned int irq)
151 imr = sysRegRead(AR5315_IMR);
154 case AR531X_MISC_IRQ_SPI:
155 imr |= AR5315_ISR_SPI;
158 case AR531X_MISC_IRQ_TIMER:
159 imr |= AR5315_ISR_TIMER;
162 case AR531X_MISC_IRQ_AHB_PROC:
163 imr |= AR5315_ISR_AHB;
166 case AR531X_MISC_IRQ_AHB_DMA:
170 case AR531X_MISC_IRQ_GPIO:
171 imr |= AR5315_ISR_GPIO;
174 case AR531X_MISC_IRQ_UART0:
175 imr |= AR5315_ISR_UART0;
179 case AR531X_MISC_IRQ_WATCHDOG:
180 imr |= AR5315_ISR_WD;
183 case AR531X_MISC_IRQ_LOCAL:
188 sysRegWrite(AR5315_IMR, imr);
189 imr=sysRegRead(AR5315_IMR); /* flush write buffer */
192 /* Disable the specified AR531X_MISC_IRQ interrupt */
194 ar5315_misc_intr_disable(unsigned int irq)
198 imr = sysRegRead(AR5315_IMR);
201 case AR531X_MISC_IRQ_SPI:
202 imr &= ~AR5315_ISR_SPI;
205 case AR531X_MISC_IRQ_TIMER:
206 imr &= (~AR5315_ISR_TIMER);
209 case AR531X_MISC_IRQ_AHB_PROC:
210 imr &= (~AR5315_ISR_AHB);
213 case AR531X_MISC_IRQ_AHB_DMA:
217 case AR531X_MISC_IRQ_GPIO:
218 imr &= ~AR5315_ISR_GPIO;
221 case AR531X_MISC_IRQ_UART0:
222 imr &= (~AR5315_ISR_UART0);
225 case AR531X_MISC_IRQ_WATCHDOG:
226 imr &= (~AR5315_ISR_WD);
229 case AR531X_MISC_IRQ_LOCAL:
234 sysRegWrite(AR5315_IMR, imr);
235 sysRegRead(AR5315_IMR); /* flush write buffer */
238 /* Turn on the specified AR531X_MISC_IRQ interrupt */
240 ar5315_misc_intr_startup(unsigned int irq)
242 ar5315_misc_intr_enable(irq);
246 /* Turn off the specified AR531X_MISC_IRQ interrupt */
248 ar5315_misc_intr_shutdown(unsigned int irq)
250 ar5315_misc_intr_disable(irq);
254 ar5315_misc_intr_ack(unsigned int irq)
256 ar5315_misc_intr_disable(irq);
260 ar5315_misc_intr_end(unsigned int irq)
262 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
263 ar5315_misc_intr_enable(irq);
266 static struct irq_chip ar5315_misc_intr_controller = {
267 .typename = "AR5315 misc",
268 .startup = ar5315_misc_intr_startup,
269 .shutdown = ar5315_misc_intr_shutdown,
270 .enable = ar5315_misc_intr_enable,
271 .disable = ar5315_misc_intr_disable,
272 .ack = ar5315_misc_intr_ack,
273 .end = ar5315_misc_intr_end,
276 static irqreturn_t ar5315_ahb_proc_handler(int cpl, void *dev_id)
278 sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
279 sysRegRead(AR5315_AHB_ERR1);
281 printk("AHB fatal error\n");
282 machine_restart("AHB error"); /* Catastrophic failure */
287 static struct irqaction ar5315_ahb_proc_interrupt = {
288 .handler = ar5315_ahb_proc_handler,
289 .flags = IRQF_DISABLED,
290 .name = "ar5315_ahb_proc_interrupt",
294 static struct irqaction cascade = {
295 .handler = no_action,
296 .flags = IRQF_DISABLED,
300 static void ar5315_gpio_intr_init(int irq_base)
304 for (i = irq_base; i < irq_base + AR531X_GPIO_IRQ_COUNT; i++) {
305 irq_desc[i].status = IRQ_DISABLED;
306 irq_desc[i].action = NULL;
307 irq_desc[i].depth = 1;
308 irq_desc[i].chip = &ar5315_gpio_intr_controller;
310 setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
311 gpiointval = sysRegRead(AR5315_GPIO_DI);
314 void ar5315_misc_intr_init(int irq_base)
318 for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
319 irq_desc[i].status = IRQ_DISABLED;
320 irq_desc[i].action = NULL;
321 irq_desc[i].depth = 1;
322 irq_desc[i].chip = &ar5315_misc_intr_controller;
324 setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt);
325 setup_irq(AR5315_IRQ_MISC_INTRS, &cascade);
326 ar5315_gpio_intr_init(AR531X_GPIO_IRQ_BASE);