2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/platform_device.h>
22 #include <linux/kernel.h>
23 #include <linux/reboot.h>
24 #include <asm/bootinfo.h>
25 #include <asm/reboot.h>
30 #include <linux/leds.h>
33 static int is_5315 = 0;
35 static struct resource ar5315_eth_res[] = {
37 .name = "eth0_membase",
38 .flags = IORESOURCE_MEM,
39 .start = AR5315_ENET0,
40 .end = AR5315_ENET0 + 0x2000,
44 .flags = IORESOURCE_IRQ,
45 .start = AR5315_IRQ_ENET0_INTRS,
46 .end = AR5315_IRQ_ENET0_INTRS,
50 static struct ar531x_eth ar5315_eth_data = {
53 .reset_base = AR5315_RESET,
54 .reset_mac = AR5315_RESET_ENET0,
55 .reset_phy = AR5315_RESET_EPHY0,
56 .phy_base = AR5315_ENET0
59 static struct platform_device ar5315_eth = {
62 .dev.platform_data = &ar5315_eth_data,
63 .resource = ar5315_eth_res,
64 .num_resources = ARRAY_SIZE(ar5315_eth_res)
67 static struct platform_device ar5315_wmac = {
69 .name = "ar531x-wmac",
70 /* FIXME: add resources */
73 static struct resource ar5315_spiflash_res[] = {
76 .flags = IORESOURCE_MEM,
77 .start = KSEG1ADDR(AR5315_SPI_READ),
78 .end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
82 .flags = IORESOURCE_MEM,
88 static struct platform_device ar5315_spiflash = {
91 .resource = ar5315_spiflash_res,
92 .num_resources = ARRAY_SIZE(ar5315_spiflash_res)
95 #ifdef CONFIG_LEDS_GPIO
96 static struct gpio_led ar5315_leds[] = {
97 { .name = "wlan", .gpio = 0, .active_low = 1, },
100 static const struct gpio_led_platform_data ar5315_led_data = {
101 .num_leds = ARRAY_SIZE(ar5315_leds),
102 .leds = (void *) ar5315_leds,
105 static struct platform_device ar5315_gpio_leds = {
109 .platform_data = (void *) &ar5315_led_data,
115 static __initdata struct platform_device *ar5315_devs[5];
119 static void *flash_regs;
121 static inline __u32 spiflash_regread32(int reg)
123 volatile __u32 *data = (__u32 *)(flash_regs + reg);
128 static inline void spiflash_regwrite32(int reg, __u32 data)
130 volatile __u32 *addr = (__u32 *)(flash_regs + reg);
135 #define SPI_FLASH_CTL 0x00
136 #define SPI_FLASH_OPCODE 0x04
137 #define SPI_FLASH_DATA 0x08
139 static __u8 spiflash_probe(void)
144 reg = spiflash_regread32(SPI_FLASH_CTL);
145 } while (reg & SPI_CTL_BUSY);
147 spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
149 reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
150 (1 << 4) | SPI_CTL_START;
152 spiflash_regwrite32(SPI_FLASH_CTL, reg);
155 reg = spiflash_regread32(SPI_FLASH_CTL);
156 } while (reg & SPI_CTL_BUSY);
158 reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
165 #define STM_8MBIT_SIGNATURE 0x13
166 #define STM_16MBIT_SIGNATURE 0x14
167 #define STM_32MBIT_SIGNATURE 0x15
168 #define STM_64MBIT_SIGNATURE 0x16
169 #define STM_128MBIT_SIGNATURE 0x17
172 static char __init *ar5315_flash_limit(void)
177 /* probe the flash chip size */
178 flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
179 sig = spiflash_probe();
183 case STM_8MBIT_SIGNATURE:
184 flash_size = 0x00100000;
186 case STM_16MBIT_SIGNATURE:
187 flash_size = 0x00200000;
189 case STM_32MBIT_SIGNATURE:
190 flash_size = 0x00400000;
192 case STM_64MBIT_SIGNATURE:
193 flash_size = 0x00800000;
195 case STM_128MBIT_SIGNATURE:
196 flash_size = 0x01000000;
200 ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
201 return (char *) ar5315_spiflash_res[0].end;
204 int __init ar5315_init_devices(void)
206 struct ar531x_config *config;
207 struct ar531x_boarddata *bcfg;
213 /* Find board configuration */
214 ar531x_find_config(ar5315_flash_limit());
215 bcfg = (struct ar531x_boarddata *) board_config;
219 /* Detect the hardware based on the device ID */
220 u32 devid = sysRegRead(AR5315_SREV) & AR5315_REV_MAJ >> AR5315_REV_MAJ_S;
223 mips_machtype = MACH_ATHEROS_AR2317;
225 /* FIXME: how can we detect AR2316? */
228 mips_machtype = MACH_ATHEROS_AR2315;
234 config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
235 config->board = board_config;
236 config->radio = radio_config;
238 config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
240 ar5315_eth_data.board_config = board_config;
241 ar5315_eth_data.macaddr = bcfg->enet0Mac;
242 ar5315_wmac.dev.platform_data = config;
244 ar5315_devs[dev++] = &ar5315_eth;
245 ar5315_devs[dev++] = &ar5315_wmac;
246 ar5315_devs[dev++] = &ar5315_spiflash;
248 #ifdef CONFIG_LEDS_GPIO
249 ar5315_leds[0].gpio = bcfg->sysLedGpio;
250 ar5315_devs[dev++] = &ar5315_gpio_leds;
253 return platform_add_devices(ar5315_devs, dev);
256 static void ar5315_halt(void)
261 static void ar5315_power_off(void)
267 static void ar5315_restart(char *command)
271 /* reset the system */
272 sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
275 * Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
277 gpio_direction_output(AR5315_RESET_GPIO, 0);
283 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
284 * to determine the predevisor value.
286 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
293 static int __initdata PLLC_DIVIDE_TABLE[5] = {
301 static unsigned int __init
302 ar5315_sys_clk(unsigned int clockCtl)
304 unsigned int pllcCtrl,cpuDiv;
305 unsigned int pllcOut,refdiv,fdiv,divby2;
308 pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
309 refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
310 refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
311 fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
312 divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
314 pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
317 /* clkm input selected */
318 switch(clockCtl & CPUCLK_CLK_SEL_M) {
321 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
324 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
331 cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
332 cpuDiv = cpuDiv * 2 ?: 1;
333 return (pllcOut/(clkDiv * cpuDiv));
336 static inline unsigned int ar5315_cpu_frequency(void)
338 return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
341 static inline unsigned int ar5315_apb_frequency(void)
343 return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
346 static void __init ar5315_time_init(void)
348 mips_hpt_frequency = ar5315_cpu_frequency() / 2;
351 void __init ar5315_prom_init(void)
356 memcfg = sysRegRead(AR5315_MEM_CFG);
357 memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
358 memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
359 memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
361 add_memory_region(0, memsize, BOOT_MEM_RAM);
363 /* Initialize it to AR2315 for now. Real detection will be done
364 * in ar5315_init_devices() */
365 mips_machtype = MACH_ATHEROS_AR2315;
368 void __init ar5315_plat_setup(void)
370 unsigned int config = read_c0_config();
372 /* Clear any lingering AHB errors */
373 write_c0_config(config & ~0x3);
374 sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
375 sysRegRead(AR5315_AHB_ERR1);
376 sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
378 board_time_init = ar5315_time_init;
380 _machine_restart = ar5315_restart;
381 _machine_halt = ar5315_halt;
382 pm_power_off = ar5315_power_off;
384 serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
387 arch_initcall(ar5315_init_devices);