2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/platform_device.h>
22 #include <linux/kernel.h>
23 #include <linux/reboot.h>
24 #include <asm/bootinfo.h>
25 #include <asm/reboot.h>
31 static int is_5315 = 0;
33 static struct resource ar5315_eth_res[] = {
35 .name = "eth0_membase",
36 .flags = IORESOURCE_MEM,
37 .start = AR5315_ENET0,
38 .end = AR5315_ENET0 + 0x2000,
42 .flags = IORESOURCE_IRQ,
43 .start = AR5315_IRQ_ENET0_INTRS,
44 .end = AR5315_IRQ_ENET0_INTRS,
48 static struct ar531x_eth ar5315_eth_data = {
51 .reset_base = AR5315_RESET,
52 .reset_mac = AR5315_RESET_ENET0,
53 .reset_phy = AR5315_RESET_EPHY0,
54 .phy_base = AR5315_ENET0
57 static struct platform_device ar5315_eth = {
60 .dev.platform_data = &ar5315_eth_data,
61 .resource = ar5315_eth_res,
62 .num_resources = ARRAY_SIZE(ar5315_eth_res)
65 static struct platform_device ar5315_wmac = {
67 .name = "ar531x-wmac",
68 /* FIXME: add resources */
71 static struct resource ar5315_spiflash_res[] = {
74 .flags = IORESOURCE_MEM,
75 .start = KSEG1ADDR(AR5315_SPI_READ),
76 .end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
80 .flags = IORESOURCE_MEM,
86 static struct platform_device ar5315_spiflash = {
89 .resource = ar5315_spiflash_res,
90 .num_resources = ARRAY_SIZE(ar5315_spiflash_res)
93 static __initdata struct platform_device *ar5315_devs[4];
97 static void *flash_regs;
99 static inline __u32 spiflash_regread32(int reg)
101 volatile __u32 *data = (__u32 *)(flash_regs + reg);
106 static inline void spiflash_regwrite32(int reg, __u32 data)
108 volatile __u32 *addr = (__u32 *)(flash_regs + reg);
113 #define SPI_FLASH_CTL 0x00
114 #define SPI_FLASH_OPCODE 0x04
115 #define SPI_FLASH_DATA 0x08
117 static __u8 spiflash_probe(void)
122 reg = spiflash_regread32(SPI_FLASH_CTL);
123 } while (reg & SPI_CTL_BUSY);
125 spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
127 reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
128 (1 << 4) | SPI_CTL_START;
130 spiflash_regwrite32(SPI_FLASH_CTL, reg);
133 reg = spiflash_regread32(SPI_FLASH_CTL);
134 } while (reg & SPI_CTL_BUSY);
136 reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
143 #define STM_8MBIT_SIGNATURE 0x13
144 #define STM_16MBIT_SIGNATURE 0x14
145 #define STM_32MBIT_SIGNATURE 0x15
146 #define STM_64MBIT_SIGNATURE 0x16
147 #define STM_128MBIT_SIGNATURE 0x17
150 static char __init *ar5315_flash_limit(void)
155 /* probe the flash chip size */
156 flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
157 sig = spiflash_probe();
161 case STM_8MBIT_SIGNATURE:
162 flash_size = 0x00100000;
164 case STM_16MBIT_SIGNATURE:
165 flash_size = 0x00200000;
167 case STM_32MBIT_SIGNATURE:
168 flash_size = 0x00400000;
170 case STM_64MBIT_SIGNATURE:
171 flash_size = 0x00800000;
173 case STM_128MBIT_SIGNATURE:
174 flash_size = 0x01000000;
178 ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
179 return (char *) ar5315_spiflash_res[0].end;
182 int __init ar5315_init_devices(void)
184 struct ar531x_config *config;
185 struct ar531x_boarddata *bcfg;
191 /* Find board configuration */
192 ar531x_find_config(ar5315_flash_limit());
193 bcfg = (struct ar531x_boarddata *) board_config;
197 /* Detect the hardware based on the device ID */
198 u32 devid = sysRegRead(AR5315_SREV) & AR5315_REV_MAJ >> AR5315_REV_MAJ_S;
201 mips_machtype = MACH_ATHEROS_AR2317;
203 /* FIXME: how can we detect AR2316? */
206 mips_machtype = MACH_ATHEROS_AR2315;
212 config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
213 config->board = board_config;
214 config->radio = radio_config;
216 config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
218 ar5315_eth_data.board_config = board_config;
219 ar5315_eth_data.macaddr = bcfg->enet0Mac;
220 ar5315_wmac.dev.platform_data = config;
222 ar5315_devs[dev++] = &ar5315_eth;
223 ar5315_devs[dev++] = &ar5315_wmac;
224 ar5315_devs[dev++] = &ar5315_spiflash;
227 return platform_add_devices(ar5315_devs, dev);
230 static void ar5315_halt(void)
235 static void ar5315_power_off(void)
241 static void ar5315_restart(char *command)
246 /* reset the system */
247 sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
250 * Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
253 reg = sysRegRead(AR5315_GPIO_DO);
254 reg &= ~(1 << AR5315_RESET_GPIO);
255 sysRegWrite(AR5315_GPIO_DO, reg);
256 (void)sysRegRead(AR5315_GPIO_DO); /* flush write to hardware */
262 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
263 * to determine the predevisor value.
265 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
272 static int __initdata PLLC_DIVIDE_TABLE[5] = {
280 static unsigned int __init
281 ar5315_sys_clk(unsigned int clockCtl)
283 unsigned int pllcCtrl,cpuDiv;
284 unsigned int pllcOut,refdiv,fdiv,divby2;
287 pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
288 refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
289 refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
290 fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
291 divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
293 pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
296 /* clkm input selected */
297 switch(clockCtl & CPUCLK_CLK_SEL_M) {
300 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
303 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
310 cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
311 cpuDiv = cpuDiv * 2 ?: 1;
312 return (pllcOut/(clkDiv * cpuDiv));
315 static inline unsigned int ar5315_cpu_frequency(void)
317 return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
320 static inline unsigned int ar5315_apb_frequency(void)
322 return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
325 static void __init ar5315_time_init(void)
327 mips_hpt_frequency = ar5315_cpu_frequency() / 2;
330 void __init ar5315_prom_init(void)
335 memcfg = sysRegRead(AR5315_MEM_CFG);
336 memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
337 memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
338 memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
340 add_memory_region(0, memsize, BOOT_MEM_RAM);
342 /* Initialize it to AR2315 for now. Real detection will be done
343 * in ar5315_init_devices() */
344 mips_machtype = MACH_ATHEROS_AR2315;
347 void __init ar5315_plat_setup(void)
349 unsigned int config = read_c0_config();
351 /* Clear any lingering AHB errors */
352 write_c0_config(config & ~0x3);
353 sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
354 sysRegRead(AR5315_AHB_ERR1);
355 sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
357 board_time_init = ar5315_time_init;
359 _machine_restart = ar5315_restart;
360 _machine_halt = ar5315_halt;
361 pm_power_off = ar5315_power_off;
363 serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
366 arch_initcall(ar5315_init_devices);