target/linux/ath79/patches-5.4/0039-MIPS-ath79-export-UART1-reference-clock.patch

   1 --- a/arch/mips/ath79/clock.c
   2 +++ b/arch/mips/ath79/clock.c
   3 @@ -40,6 +40,7 @@ static const char * const clk_names[ATH7
   4         [ATH79_CLK_AHB] = "ahb",
   5         [ATH79_CLK_REF] = "ref",
   6         [ATH79_CLK_MDIO] = "mdio",
   7 +       [ATH79_CLK_UART1] = "uart1",
   8  };
   9
  10  static const char * __init ath79_clk_name(int type)
  11 @@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo
  12         if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
  13                 ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
  14
  15 +       if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
  16 +               ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
  17 +
  18         iounmap(dpll_base);
  19  }
  20
  21 @@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(
  22         if (!clks[ATH79_CLK_MDIO])
  23                 clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
  24
  25 +       if (!clks[ATH79_CLK_UART1])
  26 +               clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
  27 +
  28         if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
  29                 pr_err("%pOF: could not register clk provider\n", np);
  30                 goto err_iounmap;
  31 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  32 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  33 @@ -348,6 +348,7 @@
  34  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  35
  36  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
  37 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL  BIT(7)
  38
  39  #define QCA953X_PLL_CPU_CONFIG_REG             0x00
  40  #define QCA953X_PLL_DDR_CONFIG_REG             0x04
  41 --- a/include/dt-bindings/clock/ath79-clk.h
  42 +++ b/include/dt-bindings/clock/ath79-clk.h
  43 @@ -11,7 +11,8 @@
  44  #define ATH79_CLK_AHB          2
  45  #define ATH79_CLK_REF          3
  46  #define ATH79_CLK_MDIO         4
  47 +#define ATH79_CLK_UART1                5
  48
  49 -#define ATH79_CLK_END          5
  50 +#define ATH79_CLK_END          6
  51
  52  #endif /* __DT_BINDINGS_ATH79_CLK_H */