target/linux/ath79/patches-5.4/0036-MIPS-ath79-remove-irq-code-from-pci.patch

   1 --- a/arch/mips/pci/pci-ar71xx.c
   2 +++ b/arch/mips/pci/pci-ar71xx.c
   3 @@ -51,11 +51,9 @@
   4  struct ar71xx_pci_controller {
   5         struct device_node *np;
   6         void __iomem *cfg_base;
   7 -       int irq;
   8         struct pci_controller pci_ctrl;
   9         struct resource io_res;
  10         struct resource mem_res;
  11 -       struct irq_domain *domain;
  12  };
  13
  14  /* Byte lane enable bits */
  15 @@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = {
  16         .write  = ar71xx_pci_write_config,
  17  };
  18
  19 -static void ar71xx_pci_irq_handler(struct irq_desc *desc)
  20 -{
  21 -       void __iomem *base = ath79_reset_base;
  22 -       struct irq_chip *chip = irq_desc_get_chip(desc);
  23 -       struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
  24 -       u32 pending;
  25 -
  26 -       chained_irq_enter(chip, desc);
  27 -       pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
  28 -                 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  29 -
  30 -       if (pending & AR71XX_PCI_INT_DEV0)
  31 -               generic_handle_irq(irq_linear_revmap(apc->domain, 1));
  32 -
  33 -       else if (pending & AR71XX_PCI_INT_DEV1)
  34 -               generic_handle_irq(irq_linear_revmap(apc->domain, 2));
  35 -
  36 -       else if (pending & AR71XX_PCI_INT_DEV2)
  37 -               generic_handle_irq(irq_linear_revmap(apc->domain, 3));
  38 -
  39 -       else if (pending & AR71XX_PCI_INT_CORE)
  40 -               generic_handle_irq(irq_linear_revmap(apc->domain, 4));
  41 -
  42 -       else
  43 -               spurious_interrupt();
  44 -       chained_irq_exit(chip, desc);
  45 -}
  46 -
  47 -static void ar71xx_pci_irq_unmask(struct irq_data *d)
  48 -{
  49 -       struct ar71xx_pci_controller *apc;
  50 -       unsigned int irq;
  51 -       void __iomem *base = ath79_reset_base;
  52 -       u32 t;
  53 -
  54 -       apc = irq_data_get_irq_chip_data(d);
  55 -       irq = irq_linear_revmap(apc->domain, d->irq);
  56 -
  57 -       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  58 -       __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  59 -
  60 -       /* flush write */
  61 -       __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  62 -}
  63 -
  64 -static void ar71xx_pci_irq_mask(struct irq_data *d)
  65 -{
  66 -       struct ar71xx_pci_controller *apc;
  67 -       unsigned int irq;
  68 -       void __iomem *base = ath79_reset_base;
  69 -       u32 t;
  70 -
  71 -       apc = irq_data_get_irq_chip_data(d);
  72 -       irq = irq_linear_revmap(apc->domain, d->irq);
  73 -
  74 -       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  75 -       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  76 -
  77 -       /* flush write */
  78 -       __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  79 -}
  80 -
  81 -static struct irq_chip ar71xx_pci_irq_chip = {
  82 -       .name           = "AR71XX PCI",
  83 -       .irq_mask       = ar71xx_pci_irq_mask,
  84 -       .irq_unmask     = ar71xx_pci_irq_unmask,
  85 -       .irq_mask_ack   = ar71xx_pci_irq_mask,
  86 -};
  87 -
  88 -static int ar71xx_pci_irq_map(struct irq_domain *d,
  89 -                             unsigned int irq, irq_hw_number_t hw)
  90 -{
  91 -       struct ar71xx_pci_controller *apc = d->host_data;
  92 -
  93 -       irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
  94 -       irq_set_chip_data(irq, apc);
  95 -
  96 -       return 0;
  97 -}
  98 -
  99 -static const struct irq_domain_ops ar71xx_pci_domain_ops = {
 100 -       .xlate = irq_domain_xlate_onecell,
 101 -       .map = ar71xx_pci_irq_map,
 102 -};
 103 -
 104 -static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
 105 -{
 106 -       void __iomem *base = ath79_reset_base;
 107 -
 108 -       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 109 -       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 110 -
 111 -       apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
 112 -                                           &ar71xx_pci_domain_ops, apc);
 113 -       irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
 114 -                                        apc);
 115 -}
 116 -
 117  static void ar71xx_pci_reset(void)
 118  {
 119         ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
 120 @@ -358,10 +258,6 @@ static int ar71xx_pci_probe(struct platf
 121         if (IS_ERR(apc->cfg_base))
 122                 return PTR_ERR(apc->cfg_base);
 123
 124 -       apc->irq = platform_get_irq(pdev, 0);
 125 -       if (apc->irq < 0)
 126 -               return -EINVAL;
 127 -
 128         ar71xx_pci_reset();
 129
 130         /* setup COMMAND register */
 131 @@ -372,8 +268,6 @@ static int ar71xx_pci_probe(struct platf
 132         /* clear bus errors */
 133         ar71xx_pci_check_error(apc, 1);
 134
 135 -       ar71xx_pci_irq_init(apc);
 136 -
 137         apc->np = pdev->dev.of_node;
 138         apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 139         apc->pci_ctrl.mem_resource = &apc->mem_res;