1 From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Mon, 25 Jun 2018 15:52:10 +0200
4 Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
6 With the driver being converted from platform_data to pure OF, we need to
9 Cc: Rob Herring <robh+dt@kernel.org>
10 Cc: devicetree@vger.kernel.org
11 Signed-off-by: John Crispin <john@phrozen.org>
13 .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++
14 1 file changed, 38 insertions(+)
15 create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
18 +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
20 +* Qualcomm Atheros AR7100 PCI express root complex
23 +- compatible: should contain "qcom,ar7100-pci" to identify the core.
24 +- reg: Should contain the register ranges as listed in the reg-names property.
25 +- reg-names: Definition: Must include the following entries
26 + - "cfg_base" IO Memory
27 +- #address-cells: set to <3>
28 +- #size-cells: set to <2>
29 +- ranges: ranges for the PCI memory and I/O regions
30 +- interrupt-map-mask and interrupt-map: standard PCI
31 + properties to define the mapping of the PCIe interface to interrupt
33 +- #interrupt-cells: set to <1>
34 +- interrupt-controller: define to enable the builtin IRQ cascade.
37 +- interrupt-parent: phandle to the MIPS IRQ controller
40 + pcie-controller@180c0000 {
41 + compatible = "qca,ar7100-pci";
42 + #address-cells = <3>;
44 + bus-range = <0x0 0x0>;
45 + reg = <0x17010000 0x100>;
46 + reg-names = "cfg_base";
47 + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
48 + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
49 + interrupt-parent = <&cpuintc>;
52 + interrupt-controller;
53 + #interrupt-cells = <1>;
55 + interrupt-map-mask = <0 0 0 1>;
56 + interrupt-map = <0 0 0 0 &pcie0 0>;