target/linux/ath79/patches-4.14/0030-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Tue, 6 Mar 2018 13:23:20 +0100
   3 Subject: [PATCH] MIPS: ath79: pass PLL base to clock init functions
   4
   5 Preparation for passing the mapped base via DT
   6
   7 Signed-off-by: Felix Fietkau <nbd@nbd.name>
   8 ---
   9
  10 --- a/arch/mips/ath79/clock.c
  11 +++ b/arch/mips/ath79/clock.c
  12 @@ -79,7 +79,7 @@ static struct clk * __init ath79_set_ff_
  13         return clk;
  14  }
  15
  16 -static void __init ar71xx_clocks_init(void)
  17 +static void __init ar71xx_clocks_init(void __iomem *pll_base)
  18  {
  19         unsigned long ref_rate;
  20         unsigned long cpu_rate;
  21 @@ -91,7 +91,7 @@ static void __init ar71xx_clocks_init(vo
  22
  23         ref_rate = AR71XX_BASE_FREQ;
  24
  25 -       pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
  26 +       pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
  27
  28         div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
  29         freq = div * ref_rate;
  30 @@ -129,13 +129,13 @@ static void __init ar724x_clk_init(struc
  31         ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
  32  }
  33
  34 -static void __init ar724x_clocks_init(void)
  35 +static void __init ar724x_clocks_init(void __iomem *pll_base)
  36  {
  37         struct clk *ref_clk;
  38
  39         ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
  40
  41 -       ar724x_clk_init(ref_clk, ath79_pll_base);
  42 +       ar724x_clk_init(ref_clk, pll_base);
  43  }
  44
  45  static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  46 @@ -196,7 +196,7 @@ static void __init ar9330_clk_init(struc
  47                          ref_div * out_div * ahb_div);
  48  }
  49
  50 -static void __init ar933x_clocks_init(void)
  51 +static void __init ar933x_clocks_init(void __iomem *pll_base)
  52  {
  53         struct clk *ref_clk;
  54         unsigned long ref_rate;
  55 @@ -233,7 +233,7 @@ static u32 __init ar934x_get_pll_freq(u3
  56         return ret;
  57  }
  58
  59 -static void __init ar934x_clocks_init(void)
  60 +static void __init ar934x_clocks_init(void __iomem *pll_base)
  61  {
  62         unsigned long ref_rate;
  63         unsigned long cpu_rate;
  64 @@ -264,7 +264,7 @@ static void __init ar934x_clocks_init(vo
  65                           AR934X_SRIF_DPLL1_REFDIV_MASK;
  66                 frac = 1 << 18;
  67         } else {
  68 -               pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
  69 +               pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
  70                 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  71                         AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
  72                 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  73 @@ -291,7 +291,7 @@ static void __init ar934x_clocks_init(vo
  74                           AR934X_SRIF_DPLL1_REFDIV_MASK;
  75                 frac = 1 << 18;
  76         } else {
  77 -               pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
  78 +               pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
  79                 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  80                           AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
  81                 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  82 @@ -306,7 +306,7 @@ static void __init ar934x_clocks_init(vo
  83         ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
  84                                       nfrac, frac, out_div);
  85
  86 -       clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
  87 +       clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
  88
  89         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  90                   AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
  91 @@ -346,7 +346,7 @@ static void __init ar934x_clocks_init(vo
  92         iounmap(dpll_base);
  93  }
  94
  95 -static void __init qca953x_clocks_init(void)
  96 +static void __init qca953x_clocks_init(void __iomem *pll_base)
  97  {
  98         unsigned long ref_rate;
  99         unsigned long cpu_rate;
 100 @@ -362,7 +362,7 @@ static void __init qca953x_clocks_init(v
 101         else
 102                 ref_rate = 25 * 1000 * 1000;
 103
 104 -       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
 105 +       pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
 106         out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 107                   QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
 108         ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 109 @@ -376,7 +376,7 @@ static void __init qca953x_clocks_init(v
 110         cpu_pll += frac * (ref_rate >> 6) / ref_div;
 111         cpu_pll /= (1 << out_div);
 112
 113 -       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
 114 +       pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
 115         out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 116                   QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
 117         ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 118 @@ -390,7 +390,7 @@ static void __init qca953x_clocks_init(v
 119         ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
 120         ddr_pll /= (1 << out_div);
 121
 122 -       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
 123 +       clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
 124
 125         postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 126                   QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 127 @@ -428,7 +428,7 @@ static void __init qca953x_clocks_init(v
 128         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 129  }
 130
 131 -static void __init qca955x_clocks_init(void)
 132 +static void __init qca955x_clocks_init(void __iomem *pll_base)
 133  {
 134         unsigned long ref_rate;
 135         unsigned long cpu_rate;
 136 @@ -444,7 +444,7 @@ static void __init qca955x_clocks_init(v
 137         else
 138                 ref_rate = 25 * 1000 * 1000;
 139
 140 -       pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
 141 +       pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
 142         out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 143                   QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
 144         ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 145 @@ -458,7 +458,7 @@ static void __init qca955x_clocks_init(v
 146         cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
 147         cpu_pll /= (1 << out_div);
 148
 149 -       pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
 150 +       pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
 151         out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 152                   QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
 153         ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 154 @@ -472,7 +472,7 @@ static void __init qca955x_clocks_init(v
 155         ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
 156         ddr_pll /= (1 << out_div);
 157
 158 -       clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
 159 +       clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
 160
 161         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 162                   QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 163 @@ -510,7 +510,7 @@ static void __init qca955x_clocks_init(v
 164         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 165  }
 166
 167 -static void __init qca956x_clocks_init(void)
 168 +static void __init qca956x_clocks_init(void __iomem *pll_base)
 169  {
 170         unsigned long ref_rate;
 171         unsigned long cpu_rate;
 172 @@ -526,13 +526,13 @@ static void __init qca956x_clocks_init(v
 173         else
 174                 ref_rate = 25 * 1000 * 1000;
 175
 176 -       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
 177 +       pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
 178         out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 179                   QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
 180         ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 181                   QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
 182
 183 -       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
 184 +       pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
 185         nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
 186                QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
 187         hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
 188 @@ -545,12 +545,12 @@ static void __init qca956x_clocks_init(v
 189         cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
 190         cpu_pll /= (1 << out_div);
 191
 192 -       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
 193 +       pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
 194         out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 195                   QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
 196         ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 197                   QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
 198 -       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
 199 +       pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
 200         nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
 201                QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
 202         hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
 203 @@ -563,7 +563,7 @@ static void __init qca956x_clocks_init(v
 204         ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
 205         ddr_pll /= (1 << out_div);
 206
 207 -       clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
 208 +       clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
 209
 210         postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 211                   QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 212 @@ -607,19 +607,19 @@ void __init ath79_clocks_init(void)
 213         const char *uart;
 214
 215         if (soc_is_ar71xx())
 216 -               ar71xx_clocks_init();
 217 +               ar71xx_clocks_init(ath79_pll_base);
 218         else if (soc_is_ar724x() || soc_is_ar913x())
 219 -               ar724x_clocks_init();
 220 +               ar724x_clocks_init(ath79_pll_base);
 221         else if (soc_is_ar933x())
 222 -               ar933x_clocks_init();
 223 +               ar933x_clocks_init(ath79_pll_base);
 224         else if (soc_is_ar934x())
 225 -               ar934x_clocks_init();
 226 +               ar934x_clocks_init(ath79_pll_base);
 227         else if (soc_is_qca953x())
 228 -               qca953x_clocks_init();
 229 +               qca953x_clocks_init(ath79_pll_base);
 230         else if (soc_is_qca955x())
 231 -               qca955x_clocks_init();
 232 +               qca955x_clocks_init(ath79_pll_base);
 233         else if (soc_is_qca956x() || soc_is_tp9343())
 234 -               qca956x_clocks_init();
 235 +               qca956x_clocks_init(ath79_pll_base);
 236         else
 237                 BUG();
 238