ath79: add tl-wr2543-v1 support
[oweals/openwrt.git] / target / linux / ath79 / patches-4.14 / 0029-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Tue, 6 Mar 2018 13:22:43 +0100
3 Subject: [PATCH] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
4  out of soc init
5
6 Preparation for reusing functions for DT
7
8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
9 ---
10
11 --- a/arch/mips/ath79/clock.c
12 +++ b/arch/mips/ath79/clock.c
13 @@ -109,9 +109,6 @@ static void __init ar71xx_clocks_init(vo
14         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
15         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
16         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
17 -
18 -       clk_add_alias("wdt", NULL, "ahb", NULL);
19 -       clk_add_alias("uart", NULL, "ahb", NULL);
20  }
21  
22  static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
23 @@ -139,9 +136,6 @@ static void __init ar724x_clocks_init(vo
24         ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
25  
26         ar724x_clk_init(ref_clk, ath79_pll_base);
27 -
28 -       clk_add_alias("wdt", NULL, "ahb", NULL);
29 -       clk_add_alias("uart", NULL, "ahb", NULL);
30  }
31  
32  static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
33 @@ -217,9 +211,6 @@ static void __init ar933x_clocks_init(vo
34         ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
35  
36         ar9330_clk_init(ref_clk, ath79_pll_base);
37 -
38 -       clk_add_alias("wdt", NULL, "ahb", NULL);
39 -       clk_add_alias("uart", NULL, "ref", NULL);
40  }
41  
42  static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
43 @@ -352,9 +343,6 @@ static void __init ar934x_clocks_init(vo
44         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
45         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
46  
47 -       clk_add_alias("wdt", NULL, "ref", NULL);
48 -       clk_add_alias("uart", NULL, "ref", NULL);
49 -
50         iounmap(dpll_base);
51  }
52  
53 @@ -438,9 +426,6 @@ static void __init qca953x_clocks_init(v
54         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
55         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
56         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
57 -
58 -       clk_add_alias("wdt", NULL, "ref", NULL);
59 -       clk_add_alias("uart", NULL, "ref", NULL);
60  }
61  
62  static void __init qca955x_clocks_init(void)
63 @@ -523,9 +508,6 @@ static void __init qca955x_clocks_init(v
64         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
65         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
66         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
67 -
68 -       clk_add_alias("wdt", NULL, "ref", NULL);
69 -       clk_add_alias("uart", NULL, "ref", NULL);
70  }
71  
72  static void __init qca956x_clocks_init(void)
73 @@ -617,13 +599,13 @@ static void __init qca956x_clocks_init(v
74         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
75         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
76         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
77 -
78 -       clk_add_alias("wdt", NULL, "ref", NULL);
79 -       clk_add_alias("uart", NULL, "ref", NULL);
80  }
81  
82  void __init ath79_clocks_init(void)
83  {
84 +       const char *wdt;
85 +       const char *uart;
86 +
87         if (soc_is_ar71xx())
88                 ar71xx_clocks_init();
89         else if (soc_is_ar724x() || soc_is_ar913x())
90 @@ -640,6 +622,20 @@ void __init ath79_clocks_init(void)
91                 qca956x_clocks_init();
92         else
93                 BUG();
94 +
95 +       if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
96 +               wdt = "ahb";
97 +               uart = "ahb";
98 +       } else if (soc_is_ar933x()) {
99 +               wdt = "ahb";
100 +               uart = "ref";
101 +       } else {
102 +               wdt = "ref";
103 +               uart = "ref";
104 +       }
105 +
106 +       clk_add_alias("wdt", NULL, wdt, NULL);
107 +       clk_add_alias("uart", NULL, uart, NULL);
108  }
109  
110  unsigned long __init