target/linux/ath79/patches-4.14/0028-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Tue, 6 Mar 2018 13:19:26 +0100
   3 Subject: [PATCH] MIPS: ath79: add helpers for setting clocks and expose
   4  the ref clock
   5
   6 Preparation for transitioning legacy the legacy clock setup code over
   7 to OF.
   8
   9 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  10 ---
  11
  12 --- a/arch/mips/ath79/clock.c
  13 +++ b/arch/mips/ath79/clock.c
  14 @@ -36,20 +36,46 @@ static struct clk_onecell_data clk_data
  15         .clk_num = ARRAY_SIZE(clks),
  16  };
  17
  18 -static struct clk *__init ath79_add_sys_clkdev(
  19 -       const char *id, unsigned long rate)
  20 +static const char * const clk_names[ATH79_CLK_END] = {
  21 +       [ATH79_CLK_CPU] = "cpu",
  22 +       [ATH79_CLK_DDR] = "ddr",
  23 +       [ATH79_CLK_AHB] = "ahb",
  24 +       [ATH79_CLK_REF] = "ref",
  25 +};
  26 +
  27 +static const char * __init ath79_clk_name(int type)
  28  {
  29 -       struct clk *clk;
  30 -       int err;
  31 +       BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
  32 +       return clk_names[type];
  33 +}
  34
  35 -       clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
  36 +static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
  37 +{
  38         if (IS_ERR(clk))
  39 -               panic("failed to allocate %s clock structure", id);
  40 +               panic("failed to allocate %s clock structure", clk_names[type]);
  41
  42 -       err = clk_register_clkdev(clk, id, NULL);
  43 -       if (err)
  44 -               panic("unable to register %s clock device", id);
  45 +       clks[type] = clk;
  46 +       clk_register_clkdev(clk, name, NULL);
  47 +}
  48
  49 +static struct clk * __init ath79_set_clk(int type, unsigned long rate)
  50 +{
  51 +       const char *name = ath79_clk_name(type);
  52 +       struct clk *clk;
  53 +
  54 +       clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
  55 +       __ath79_set_clk(type, name, clk);
  56 +       return clk;
  57 +}
  58 +
  59 +static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
  60 +                                           unsigned int mult, unsigned int div)
  61 +{
  62 +       const char *name = ath79_clk_name(type);
  63 +       struct clk *clk;
  64 +
  65 +       clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
  66 +       __ath79_set_clk(type, name, clk);
  67         return clk;
  68  }
  69
  70 @@ -79,27 +105,15 @@ static void __init ar71xx_clocks_init(vo
  71         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
  72         ahb_rate = cpu_rate / div;
  73
  74 -       ath79_add_sys_clkdev("ref", ref_rate);
  75 -       clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
  76 -       clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
  77 -       clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
  78 +       ath79_set_clk(ATH79_CLK_REF, ref_rate);
  79 +       ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
  80 +       ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  81 +       ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  82
  83         clk_add_alias("wdt", NULL, "ahb", NULL);
  84         clk_add_alias("uart", NULL, "ahb", NULL);
  85  }
  86
  87 -static struct clk * __init ath79_reg_ffclk(const char *name,
  88 -               const char *parent_name, unsigned int mult, unsigned int div)
  89 -{
  90 -       struct clk *clk;
  91 -
  92 -       clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
  93 -       if (IS_ERR(clk))
  94 -               panic("failed to allocate %s clock structure", name);
  95 -
  96 -       return clk;
  97 -}
  98 -
  99  static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
 100  {
 101         u32 pll;
 102 @@ -113,24 +127,19 @@ static void __init ar724x_clk_init(struc
 103         ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 104         ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 105
 106 -       clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
 107 -       clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
 108 -       clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
 109 +       ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
 110 +       ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
 111 +       ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
 112  }
 113
 114  static void __init ar724x_clocks_init(void)
 115  {
 116         struct clk *ref_clk;
 117
 118 -       ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
 119 +       ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
 120
 121         ar724x_clk_init(ref_clk, ath79_pll_base);
 122
 123 -       /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
 124 -       clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
 125 -       clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
 126 -       clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
 127 -
 128         clk_add_alias("wdt", NULL, "ahb", NULL);
 129         clk_add_alias("uart", NULL, "ahb", NULL);
 130  }
 131 @@ -185,12 +194,12 @@ static void __init ar9330_clk_init(struc
 132                      AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
 133         }
 134
 135 -       clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
 136 -                                       ninit_mul, ref_div * out_div * cpu_div);
 137 -       clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
 138 -                                       ninit_mul, ref_div * out_div * ddr_div);
 139 -       clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
 140 -                                       ninit_mul, ref_div * out_div * ahb_div);
 141 +       ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
 142 +                        ref_div * out_div * cpu_div);
 143 +       ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
 144 +                        ref_div * out_div * ddr_div);
 145 +       ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
 146 +                        ref_div * out_div * ahb_div);
 147  }
 148
 149  static void __init ar933x_clocks_init(void)
 150 @@ -205,15 +214,10 @@ static void __init ar933x_clocks_init(vo
 151         else
 152                 ref_rate = (25 * 1000 * 1000);
 153
 154 -       ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
 155 +       ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
 156
 157         ar9330_clk_init(ref_clk, ath79_pll_base);
 158
 159 -       /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
 160 -       clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
 161 -       clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
 162 -       clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
 163 -
 164         clk_add_alias("wdt", NULL, "ahb", NULL);
 165         clk_add_alias("uart", NULL, "ref", NULL);
 166  }
 167 @@ -343,10 +347,10 @@ static void __init ar934x_clocks_init(vo
 168         else
 169                 ahb_rate = cpu_pll / (postdiv + 1);
 170
 171 -       ath79_add_sys_clkdev("ref", ref_rate);
 172 -       clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
 173 -       clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
 174 -       clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
 175 +       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 176 +       ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 177 +       ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 178 +       ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 179
 180         clk_add_alias("wdt", NULL, "ref", NULL);
 181         clk_add_alias("uart", NULL, "ref", NULL);
 182 @@ -430,10 +434,10 @@ static void __init qca953x_clocks_init(v
 183         else
 184                 ahb_rate = cpu_pll / (postdiv + 1);
 185
 186 -       ath79_add_sys_clkdev("ref", ref_rate);
 187 -       ath79_add_sys_clkdev("cpu", cpu_rate);
 188 -       ath79_add_sys_clkdev("ddr", ddr_rate);
 189 -       ath79_add_sys_clkdev("ahb", ahb_rate);
 190 +       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 191 +       ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 192 +       ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 193 +       ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 194
 195         clk_add_alias("wdt", NULL, "ref", NULL);
 196         clk_add_alias("uart", NULL, "ref", NULL);
 197 @@ -515,10 +519,10 @@ static void __init qca955x_clocks_init(v
 198         else
 199                 ahb_rate = cpu_pll / (postdiv + 1);
 200
 201 -       ath79_add_sys_clkdev("ref", ref_rate);
 202 -       clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
 203 -       clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
 204 -       clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
 205 +       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 206 +       ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 207 +       ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 208 +       ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 209
 210         clk_add_alias("wdt", NULL, "ref", NULL);
 211         clk_add_alias("uart", NULL, "ref", NULL);
 212 @@ -609,10 +613,10 @@ static void __init qca956x_clocks_init(v
 213         else
 214                 ahb_rate = cpu_pll / (postdiv + 1);
 215
 216 -       ath79_add_sys_clkdev("ref", ref_rate);
 217 -       ath79_add_sys_clkdev("cpu", cpu_rate);
 218 -       ath79_add_sys_clkdev("ddr", ddr_rate);
 219 -       ath79_add_sys_clkdev("ahb", ahb_rate);
 220 +       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 221 +       ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 222 +       ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 223 +       ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 224
 225         clk_add_alias("wdt", NULL, "ref", NULL);
 226         clk_add_alias("uart", NULL, "ref", NULL);
 227 --- a/include/dt-bindings/clock/ath79-clk.h
 228 +++ b/include/dt-bindings/clock/ath79-clk.h
 229 @@ -13,7 +13,8 @@
 230  #define ATH79_CLK_CPU          0
 231  #define ATH79_CLK_DDR          1
 232  #define ATH79_CLK_AHB          2
 233 +#define ATH79_CLK_REF          3
 234
 235 -#define ATH79_CLK_END          3
 236 +#define ATH79_CLK_END          4
 237
 238  #endif /* __DT_BINDINGS_ATH79_CLK_H */