target/linux/ath79/patches-4.14/0025-MIPS-ath79-drop-irq.c.patch

   1 From 08b9cad7da5d981d595fe6d76e9675f85e23e688 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 6 Mar 2018 09:57:15 +0100
   4 Subject: [PATCH 25/27] MIPS: ath79: drop irq.c
   5
   6 all IRQ init code will flow via OF based irq chips.
   7
   8 Signed-off-by: John Crispin <john@phrozen.org>
   9 ---
  10  arch/mips/ath79/Makefile |   2 +-
  11  arch/mips/ath79/irq.c    | 285 -----------------------------------------------
  12  arch/mips/ath79/setup.c  |   6 +
  13  3 files changed, 7 insertions(+), 286 deletions(-)
  14  delete mode 100644 arch/mips/ath79/irq.c
  15
  16 --- a/arch/mips/ath79/Makefile
  17 +++ b/arch/mips/ath79/Makefile
  18 @@ -8,7 +8,7 @@
  19  # under the terms of the GNU General Public License version 2 as published
  20  # by the Free Software Foundation.
  21
  22 -obj-y  := prom.o setup.o irq.o common.o clock.o
  23 +obj-y  := prom.o setup.o common.o clock.o
  24
  25  obj-$(CONFIG_EARLY_PRINTK)             += early_printk.o
  26
  27 --- a/arch/mips/ath79/irq.c
  28 +++ /dev/null
  29 @@ -1,285 +0,0 @@
  30 -/*
  31 - *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
  32 - *
  33 - *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  34 - *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  35 - *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  36 - *
  37 - *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
  38 - *
  39 - *  This program is free software; you can redistribute it and/or modify it
  40 - *  under the terms of the GNU General Public License version 2 as published
  41 - *  by the Free Software Foundation.
  42 - */
  43 -
  44 -#include <linux/kernel.h>
  45 -#include <linux/init.h>
  46 -#include <linux/interrupt.h>
  47 -#include <linux/irqchip.h>
  48 -#include <linux/of_irq.h>
  49 -
  50 -#include <asm/irq_cpu.h>
  51 -#include <asm/mipsregs.h>
  52 -
  53 -#include <asm/mach-ath79/ath79.h>
  54 -#include <asm/mach-ath79/ar71xx_regs.h>
  55 -#include "common.h"
  56 -#include "machtypes.h"
  57 -
  58 -
  59 -static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
  60 -{
  61 -       u32 status;
  62 -
  63 -       status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
  64 -
  65 -       if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
  66 -               ath79_ddr_wb_flush(3);
  67 -               generic_handle_irq(ATH79_IP2_IRQ(0));
  68 -       } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
  69 -               ath79_ddr_wb_flush(4);
  70 -               generic_handle_irq(ATH79_IP2_IRQ(1));
  71 -       } else {
  72 -               spurious_interrupt();
  73 -       }
  74 -}
  75 -
  76 -static void ar934x_ip2_irq_init(void)
  77 -{
  78 -       int i;
  79 -
  80 -       for (i = ATH79_IP2_IRQ_BASE;
  81 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  82 -               irq_set_chip_and_handler(i, &dummy_irq_chip,
  83 -                                        handle_level_irq);
  84 -
  85 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  86 -}
  87 -
  88 -static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
  89 -{
  90 -       u32 status;
  91 -
  92 -       status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
  93 -
  94 -       if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
  95 -               ath79_ddr_wb_flush(3);
  96 -               generic_handle_irq(ATH79_IP2_IRQ(0));
  97 -       } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
  98 -               ath79_ddr_wb_flush(4);
  99 -               generic_handle_irq(ATH79_IP2_IRQ(1));
 100 -       } else {
 101 -               spurious_interrupt();
 102 -       }
 103 -}
 104 -
 105 -static void qca953x_irq_init(void)
 106 -{
 107 -       int i;
 108 -
 109 -       for (i = ATH79_IP2_IRQ_BASE;
 110 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 111 -               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 112 -
 113 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
 114 -}
 115 -
 116 -static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
 117 -{
 118 -       u32 status;
 119 -
 120 -       status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
 121 -       status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
 122 -
 123 -       if (status == 0) {
 124 -               spurious_interrupt();
 125 -               return;
 126 -       }
 127 -
 128 -       if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
 129 -               /* TODO: flush DDR? */
 130 -               generic_handle_irq(ATH79_IP2_IRQ(0));
 131 -       }
 132 -
 133 -       if (status & QCA955X_EXT_INT_WMAC_ALL) {
 134 -               /* TODO: flush DDR? */
 135 -               generic_handle_irq(ATH79_IP2_IRQ(1));
 136 -       }
 137 -}
 138 -
 139 -static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
 140 -{
 141 -       u32 status;
 142 -
 143 -       status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
 144 -       status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
 145 -                 QCA955X_EXT_INT_USB1 |
 146 -                 QCA955X_EXT_INT_USB2;
 147 -
 148 -       if (status == 0) {
 149 -               spurious_interrupt();
 150 -               return;
 151 -       }
 152 -
 153 -       if (status & QCA955X_EXT_INT_USB1) {
 154 -               /* TODO: flush DDR? */
 155 -               generic_handle_irq(ATH79_IP3_IRQ(0));
 156 -       }
 157 -
 158 -       if (status & QCA955X_EXT_INT_USB2) {
 159 -               /* TODO: flush DDR? */
 160 -               generic_handle_irq(ATH79_IP3_IRQ(1));
 161 -       }
 162 -
 163 -       if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
 164 -               /* TODO: flush DDR? */
 165 -               generic_handle_irq(ATH79_IP3_IRQ(2));
 166 -       }
 167 -}
 168 -
 169 -static void qca955x_irq_init(void)
 170 -{
 171 -       int i;
 172 -
 173 -       for (i = ATH79_IP2_IRQ_BASE;
 174 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 175 -               irq_set_chip_and_handler(i, &dummy_irq_chip,
 176 -                                        handle_level_irq);
 177 -
 178 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
 179 -
 180 -       for (i = ATH79_IP3_IRQ_BASE;
 181 -            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 182 -               irq_set_chip_and_handler(i, &dummy_irq_chip,
 183 -                                        handle_level_irq);
 184 -
 185 -       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
 186 -}
 187 -
 188 -static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
 189 -{
 190 -       u32 status;
 191 -
 192 -       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 193 -       status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
 194 -
 195 -       if (status == 0) {
 196 -               spurious_interrupt();
 197 -               return;
 198 -       }
 199 -
 200 -       if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
 201 -               /* TODO: flush DDR? */
 202 -               generic_handle_irq(ATH79_IP2_IRQ(0));
 203 -       }
 204 -
 205 -       if (status & QCA956X_EXT_INT_WMAC_ALL) {
 206 -               /* TODO: flsuh DDR? */
 207 -               generic_handle_irq(ATH79_IP2_IRQ(1));
 208 -       }
 209 -}
 210 -
 211 -static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
 212 -{
 213 -       u32 status;
 214 -
 215 -       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 216 -       status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
 217 -                 QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
 218 -
 219 -       if (status == 0) {
 220 -               spurious_interrupt();
 221 -               return;
 222 -       }
 223 -
 224 -       if (status & QCA956X_EXT_INT_USB1) {
 225 -               /* TODO: flush DDR? */
 226 -               generic_handle_irq(ATH79_IP3_IRQ(0));
 227 -       }
 228 -
 229 -       if (status & QCA956X_EXT_INT_USB2) {
 230 -               /* TODO: flush DDR? */
 231 -               generic_handle_irq(ATH79_IP3_IRQ(1));
 232 -       }
 233 -
 234 -       if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
 235 -               /* TODO: flush DDR? */
 236 -               generic_handle_irq(ATH79_IP3_IRQ(2));
 237 -       }
 238 -}
 239 -
 240 -static void qca956x_enable_timer_cb(void) {
 241 -       u32 misc;
 242 -
 243 -       misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 244 -       misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
 245 -       ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
 246 -}
 247 -
 248 -static void qca956x_irq_init(void)
 249 -{
 250 -       int i;
 251 -
 252 -       for (i = ATH79_IP2_IRQ_BASE;
 253 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 254 -               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 255 -
 256 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 257 -
 258 -       for (i = ATH79_IP3_IRQ_BASE;
 259 -            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 260 -               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 261 -
 262 -       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 263 -
 264 -       /* QCA956x timer init workaround has to be applied right before setting
 265 -        * up the clock. Else, there will be no jiffies */
 266 -       late_time_init = &qca956x_enable_timer_cb;
 267 -}
 268 -
 269 -void __init arch_init_irq(void)
 270 -{
 271 -       unsigned irq_wb_chan2 = -1;
 272 -       unsigned irq_wb_chan3 = -1;
 273 -       bool misc_is_ar71xx;
 274 -
 275 -       if (mips_machtype == ATH79_MACH_GENERIC_OF) {
 276 -               irqchip_init();
 277 -               return;
 278 -       }
 279 -
 280 -       if (soc_is_ar71xx() || soc_is_ar724x() ||
 281 -           soc_is_ar913x() || soc_is_ar933x()) {
 282 -               irq_wb_chan2 = 3;
 283 -               irq_wb_chan3 = 2;
 284 -       } else if (soc_is_ar934x() || soc_is_qca953x()) {
 285 -               irq_wb_chan3 = 2;
 286 -       }
 287 -
 288 -       ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
 289 -
 290 -       if (soc_is_ar71xx() || soc_is_ar913x())
 291 -               misc_is_ar71xx = true;
 292 -       else if (soc_is_ar724x() ||
 293 -                soc_is_ar933x() ||
 294 -                soc_is_ar934x() ||
 295 -                soc_is_qca953x() ||
 296 -                soc_is_qca955x() ||
 297 -                soc_is_qca956x() ||
 298 -                soc_is_tp9343())
 299 -               misc_is_ar71xx = false;
 300 -       else
 301 -               BUG();
 302 -       ath79_misc_irq_init(
 303 -               ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
 304 -               ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
 305 -
 306 -       if (soc_is_ar934x())
 307 -               ar934x_ip2_irq_init();
 308 -       else if (soc_is_qca953x())
 309 -               qca953x_irq_init();
 310 -       else if (soc_is_qca955x())
 311 -               qca955x_irq_init();
 312 -       else if (soc_is_qca956x() || soc_is_tp9343())
 313 -               qca956x_irq_init();
 314 -}
 315 --- a/arch/mips/ath79/setup.c
 316 +++ b/arch/mips/ath79/setup.c
 317 @@ -19,6 +19,7 @@
 318  #include <linux/clk.h>
 319  #include <linux/clk-provider.h>
 320  #include <linux/of_fdt.h>
 321 +#include <linux/irqchip.h>
 322
 323  #include <asm/bootinfo.h>
 324  #include <asm/idle.h>
 325 @@ -310,6 +311,11 @@ void __init plat_time_init(void)
 326         mips_hpt_frequency = cpu_clk_rate / 2;
 327  }
 328
 329 +void __init arch_init_irq(void)
 330 +{
 331 +       irqchip_init();
 332 +}
 333 +
 334  static int __init ath79_setup(void)
 335  {
 336         if  (mips_machtype == ATH79_MACH_GENERIC_OF)