target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch

   1 From cc5a306038b7956b5736a70696dddaaf3792df76 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 6 Mar 2018 09:22:49 +0100
   4 Subject: [PATCH 20/27] MIPS: ath79: turn pci-ar71xx driver into a pure OF
   5  driver
   6
   7 Signed-off-by: John Crispin <john@phrozen.org>
   8 ---
   9  arch/mips/pci/pci-ar71xx.c | 81 +++++++++++++++++++++++-----------------------
  10  1 file changed, 40 insertions(+), 41 deletions(-)
  11
  12 --- a/arch/mips/pci/pci-ar71xx.c
  13 +++ b/arch/mips/pci/pci-ar71xx.c
  14 @@ -18,8 +18,11 @@
  15  #include <linux/pci.h>
  16  #include <linux/pci_regs.h>
  17  #include <linux/interrupt.h>
  18 +#include <linux/irqchip/chained_irq.h>
  19  #include <linux/init.h>
  20  #include <linux/platform_device.h>
  21 +#include <linux/of_irq.h>
  22 +#include <linux/of_pci.h>
  23
  24  #include <asm/mach-ath79/ar71xx_regs.h>
  25  #include <asm/mach-ath79/ath79.h>
  26 @@ -49,12 +52,13 @@
  27  #define AR71XX_PCI_IRQ_COUNT           5
  28
  29  struct ar71xx_pci_controller {
  30 +       struct device_node *np;
  31         void __iomem *cfg_base;
  32         int irq;
  33 -       int irq_base;
  34         struct pci_controller pci_ctrl;
  35         struct resource io_res;
  36         struct resource mem_res;
  37 +       struct irq_domain *domain;
  38  };
  39
  40  /* Byte lane enable bits */
  41 @@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
  42
  43  static void ar71xx_pci_irq_handler(struct irq_desc *desc)
  44  {
  45 -       struct ar71xx_pci_controller *apc;
  46         void __iomem *base = ath79_reset_base;
  47 +       struct irq_chip *chip = irq_desc_get_chip(desc);
  48 +       struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
  49         u32 pending;
  50
  51 -       apc = irq_desc_get_handler_data(desc);
  52 -
  53 +       chained_irq_enter(chip, desc);
  54         pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
  55                   __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  56
  57         if (pending & AR71XX_PCI_INT_DEV0)
  58 -               generic_handle_irq(apc->irq_base + 0);
  59 +               generic_handle_irq(irq_linear_revmap(apc->domain, 1));
  60
  61         else if (pending & AR71XX_PCI_INT_DEV1)
  62 -               generic_handle_irq(apc->irq_base + 1);
  63 +               generic_handle_irq(irq_linear_revmap(apc->domain, 2));
  64
  65         else if (pending & AR71XX_PCI_INT_DEV2)
  66 -               generic_handle_irq(apc->irq_base + 2);
  67 +               generic_handle_irq(irq_linear_revmap(apc->domain, 3));
  68
  69         else if (pending & AR71XX_PCI_INT_CORE)
  70 -               generic_handle_irq(apc->irq_base + 4);
  71 +               generic_handle_irq(irq_linear_revmap(apc->domain, 4));
  72
  73         else
  74                 spurious_interrupt();
  75 +       chained_irq_exit(chip, desc);
  76  }
  77
  78  static void ar71xx_pci_irq_unmask(struct irq_data *d)
  79 @@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct
  80         u32 t;
  81
  82         apc = irq_data_get_irq_chip_data(d);
  83 -       irq = d->irq - apc->irq_base;
  84 +       irq = irq_linear_revmap(apc->domain, d->irq);
  85
  86         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  87         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  88 @@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i
  89         u32 t;
  90
  91         apc = irq_data_get_irq_chip_data(d);
  92 -       irq = d->irq - apc->irq_base;
  93 +       irq = irq_linear_revmap(apc->domain, d->irq);
  94
  95         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  96         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  97 @@ -294,24 +299,30 @@ static struct irq_chip ar71xx_pci_irq_ch
  98         .irq_mask_ack   = ar71xx_pci_irq_mask,
  99  };
 100
 101 +static int ar71xx_pci_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 102 +{
 103 +       struct ar71xx_pci_controller *apc = d->host_data;
 104 +
 105 +       irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
 106 +       irq_set_chip_data(irq, apc);
 107 +
 108 +       return 0;
 109 +}
 110 +
 111 +static const struct irq_domain_ops ar71xx_pci_domain_ops = {
 112 +       .xlate = irq_domain_xlate_onecell,
 113 +       .map = ar71xx_pci_irq_map,
 114 +};
 115 +
 116  static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
 117  {
 118         void __iomem *base = ath79_reset_base;
 119 -       int i;
 120
 121         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 122         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 123
 124 -       BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
 125 -
 126 -       apc->irq_base = ATH79_PCI_IRQ_BASE;
 127 -       for (i = apc->irq_base;
 128 -            i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
 129 -               irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
 130 -                                        handle_level_irq);
 131 -               irq_set_chip_data(i, apc);
 132 -       }
 133 -
 134 +       apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
 135 +                                           &ar71xx_pci_domain_ops, apc);
 136         irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
 137                                          apc);
 138  }
 139 @@ -328,6 +339,11 @@ static void ar71xx_pci_reset(void)
 140         mdelay(100);
 141  }
 142
 143 +static const struct of_device_id ar71xx_pci_ids[] = {
 144 +       { .compatible = "qca,ar7100-pci" },
 145 +       {},
 146 +};
 147 +
 148  static int ar71xx_pci_probe(struct platform_device *pdev)
 149  {
 150         struct ar71xx_pci_controller *apc;
 151 @@ -348,26 +364,6 @@ static int ar71xx_pci_probe(struct platf
 152         if (apc->irq < 0)
 153                 return -EINVAL;
 154
 155 -       res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
 156 -       if (!res)
 157 -               return -EINVAL;
 158 -
 159 -       apc->io_res.parent = res;
 160 -       apc->io_res.name = "PCI IO space";
 161 -       apc->io_res.start = res->start;
 162 -       apc->io_res.end = res->end;
 163 -       apc->io_res.flags = IORESOURCE_IO;
 164 -
 165 -       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
 166 -       if (!res)
 167 -               return -EINVAL;
 168 -
 169 -       apc->mem_res.parent = res;
 170 -       apc->mem_res.name = "PCI memory space";
 171 -       apc->mem_res.start = res->start;
 172 -       apc->mem_res.end = res->end;
 173 -       apc->mem_res.flags = IORESOURCE_MEM;
 174 -
 175         ar71xx_pci_reset();
 176
 177         /* setup COMMAND register */
 178 @@ -380,9 +376,11 @@ static int ar71xx_pci_probe(struct platf
 179
 180         ar71xx_pci_irq_init(apc);
 181
 182 +       apc->np = pdev->dev.of_node;
 183         apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 184         apc->pci_ctrl.mem_resource = &apc->mem_res;
 185         apc->pci_ctrl.io_resource = &apc->io_res;
 186 +       pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
 187
 188         register_pci_controller(&apc->pci_ctrl);
 189
 190 @@ -393,6 +391,7 @@ static struct platform_driver ar71xx_pci
 191         .probe = ar71xx_pci_probe,
 192         .driver = {
 193                 .name = "ar71xx-pci",
 194 +               .of_match_table = of_match_ptr(ar71xx_pci_ids),
 195         },
 196  };
 197