target/linux/ath79/patches-4.14/0017-MIPS-ath79-add-support-for-qca956x-soc.patch

   1 From 6aeb24b9508bbe91f89cd4eb21d0d7582d971146 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <hackpascal@gmail.com>
   3 Date: Tue, 6 Mar 2018 08:48:31 +0100
   4 Subject: [PATCH 17/27] MIPS: ath79: add support for qca956x soc
   5
   6 This patch adds soc support for QCA9561 and TP9343.
   7 TP9343 is a reduced version of QCA9561, which can be found in TP-LINK routers in China.
   8 The qca956x_wmac has not yet been supported by ath9k.
   9
  10 tested on TL-WDR6500 and TL-WR882N v1 (Chinese version)
  11
  12 Signed-off-by: Weijie Gao <hackpascal@gmail.com>
  13 ---
  14  arch/mips/ath79/Kconfig                  |  2 +-
  15  arch/mips/ath79/clock.c                  | 96 ++++++++++++++++++++++++++++++++
  16  arch/mips/ath79/common.c                 |  4 ++
  17  arch/mips/ath79/dev-common.c             |  7 ++-
  18  arch/mips/ath79/early_printk.c           |  2 +
  19  arch/mips/ath79/irq.c                    | 87 ++++++++++++++++++++++++++++-
  20  arch/mips/ath79/pci.c                    | 12 ++++
  21  arch/mips/ath79/setup.c                  | 17 +++++-
  22  arch/mips/include/asm/mach-ath79/ath79.h | 22 ++++++++
  23  9 files changed, 245 insertions(+), 4 deletions(-)
  24
  25 diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
  26 index b03f5c8b9d1e..ad56cdbc8abd 100644
  27 --- a/arch/mips/ath79/Kconfig
  28 +++ b/arch/mips/ath79/Kconfig
  29 @@ -119,7 +119,7 @@ config ATH79_DEV_USB
  30         def_bool n
  31
  32  config ATH79_DEV_WMAC
  33 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  34 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
  35         def_bool n
  36
  37  endif
  38 diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
  39 index b9595b2d1b65..65701b45fb1b 100644
  40 --- a/arch/mips/ath79/clock.c
  41 +++ b/arch/mips/ath79/clock.c
  42 @@ -525,6 +525,100 @@ static void __init qca955x_clocks_init(void)
  43         clk_add_alias("uart", NULL, "ref", NULL);
  44  }
  45
  46 +static void __init qca956x_clocks_init(void)
  47 +{
  48 +       unsigned long ref_rate;
  49 +       unsigned long cpu_rate;
  50 +       unsigned long ddr_rate;
  51 +       unsigned long ahb_rate;
  52 +       u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
  53 +       u32 cpu_pll, ddr_pll;
  54 +       u32 bootstrap;
  55 +
  56 +       bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  57 +       if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
  58 +               ref_rate = 40 * 1000 * 1000;
  59 +       else
  60 +               ref_rate = 25 * 1000 * 1000;
  61 +
  62 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
  63 +       out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  64 +                 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
  65 +       ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  66 +                 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
  67 +
  68 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
  69 +       nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
  70 +              QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
  71 +       hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
  72 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
  73 +       lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
  74 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
  75 +
  76 +       cpu_pll = nint * ref_rate / ref_div;
  77 +       cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  78 +       cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
  79 +       cpu_pll /= (1 << out_div);
  80 +
  81 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
  82 +       out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  83 +                 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
  84 +       ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  85 +                 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
  86 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
  87 +       nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
  88 +              QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
  89 +       hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
  90 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
  91 +       lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
  92 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
  93 +
  94 +       ddr_pll = nint * ref_rate / ref_div;
  95 +       ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  96 +       ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
  97 +       ddr_pll /= (1 << out_div);
  98 +
  99 +       clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
 100 +
 101 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 102 +                 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 103 +
 104 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
 105 +               cpu_rate = ref_rate;
 106 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
 107 +               cpu_rate = ddr_pll / (postdiv + 1);
 108 +       else
 109 +               cpu_rate = cpu_pll / (postdiv + 1);
 110 +
 111 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 112 +                 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 113 +
 114 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 115 +               ddr_rate = ref_rate;
 116 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
 117 +               ddr_rate = cpu_pll / (postdiv + 1);
 118 +       else
 119 +               ddr_rate = ddr_pll / (postdiv + 1);
 120 +
 121 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 122 +                 QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 123 +
 124 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 125 +               ahb_rate = ref_rate;
 126 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 127 +               ahb_rate = ddr_pll / (postdiv + 1);
 128 +       else
 129 +               ahb_rate = cpu_pll / (postdiv + 1);
 130 +
 131 +       ath79_add_sys_clkdev("ref", ref_rate);
 132 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 133 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 134 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 135 +
 136 +       clk_add_alias("wdt", NULL, "ref", NULL);
 137 +       clk_add_alias("uart", NULL, "ref", NULL);
 138 +}
 139 +
 140  void __init ath79_clocks_init(void)
 141  {
 142         if (soc_is_ar71xx())
 143 @@ -539,6 +633,8 @@ void __init ath79_clocks_init(void)
 144                 qca953x_clocks_init();
 145         else if (soc_is_qca955x())
 146                 qca955x_clocks_init();
 147 +       else if (soc_is_qca956x() || soc_is_tp9343())
 148 +               qca956x_clocks_init();
 149         else
 150                 BUG();
 151  }
 152 diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
 153 index a485a7c35b9b..fc3438150b3e 100644
 154 --- a/arch/mips/ath79/common.c
 155 +++ b/arch/mips/ath79/common.c
 156 @@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
 157                 reg = QCA953X_RESET_REG_RESET_MODULE;
 158         else if (soc_is_qca955x())
 159                 reg = QCA955X_RESET_REG_RESET_MODULE;
 160 +       else if (soc_is_qca956x() || soc_is_tp9343())
 161 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 162         else
 163                 panic("Reset register not defined for this SOC");
 164
 165 @@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
 166                 reg = QCA953X_RESET_REG_RESET_MODULE;
 167         else if (soc_is_qca955x())
 168                 reg = QCA955X_RESET_REG_RESET_MODULE;
 169 +       else if (soc_is_qca956x() || soc_is_tp9343())
 170 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 171         else
 172                 panic("Reset register not defined for this SOC");
 173
 174 diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
 175 index 99d8b88f1e6d..ac8bfe86b656 100644
 176 --- a/arch/mips/ath79/dev-common.c
 177 +++ b/arch/mips/ath79/dev-common.c
 178 @@ -86,7 +86,9 @@ void __init ath79_register_uart(void)
 179             soc_is_ar913x() ||
 180             soc_is_ar934x() ||
 181             soc_is_qca953x() ||
 182 -           soc_is_qca955x()) {
 183 +           soc_is_qca955x() ||
 184 +           soc_is_qca956x() ||
 185 +           soc_is_tp9343()) {
 186                 ath79_uart_data[0].uartclk = uart_clk_rate;
 187                 platform_device_register(&ath79_uart_device);
 188         } else if (soc_is_ar933x()) {
 189 @@ -155,6 +157,9 @@ void __init ath79_gpio_init(void)
 190         } else if (soc_is_qca955x()) {
 191                 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
 192                 ath79_gpio_pdata.oe_inverted = 1;
 193 +       } else if (soc_is_qca956x() || soc_is_tp9343()) {
 194 +               ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
 195 +               ath79_gpio_pdata.oe_inverted = 1;
 196         } else {
 197                 BUG();
 198         }
 199 diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
 200 index cc00839b7181..2024a0bb9144 100644
 201 --- a/arch/mips/ath79/early_printk.c
 202 +++ b/arch/mips/ath79/early_printk.c
 203 @@ -120,6 +120,8 @@ static void prom_putchar_init(void)
 204         case REV_ID_MAJOR_QCA9533_V2:
 205         case REV_ID_MAJOR_QCA9556:
 206         case REV_ID_MAJOR_QCA9558:
 207 +       case REV_ID_MAJOR_TP9343:
 208 +       case REV_ID_MAJOR_QCA956X:
 209                 _prom_putchar = prom_putchar_ar71xx;
 210                 break;
 211
 212 diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
 213 index 756b5aee3500..58d17ef6f58f 100644
 214 --- a/arch/mips/ath79/irq.c
 215 +++ b/arch/mips/ath79/irq.c
 216 @@ -156,6 +156,87 @@ static void qca955x_irq_init(void)
 217         irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
 218  }
 219
 220 +static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
 221 +{
 222 +       u32 status;
 223 +
 224 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 225 +       status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
 226 +
 227 +       if (status == 0) {
 228 +               spurious_interrupt();
 229 +               return;
 230 +       }
 231 +
 232 +       if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
 233 +               /* TODO: flush DDR? */
 234 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 235 +       }
 236 +
 237 +       if (status & QCA956X_EXT_INT_WMAC_ALL) {
 238 +               /* TODO: flsuh DDR? */
 239 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 240 +       }
 241 +}
 242 +
 243 +static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
 244 +{
 245 +       u32 status;
 246 +
 247 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 248 +       status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
 249 +                 QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
 250 +
 251 +       if (status == 0) {
 252 +               spurious_interrupt();
 253 +               return;
 254 +       }
 255 +
 256 +       if (status & QCA956X_EXT_INT_USB1) {
 257 +               /* TODO: flush DDR? */
 258 +               generic_handle_irq(ATH79_IP3_IRQ(0));
 259 +       }
 260 +
 261 +       if (status & QCA956X_EXT_INT_USB2) {
 262 +               /* TODO: flush DDR? */
 263 +               generic_handle_irq(ATH79_IP3_IRQ(1));
 264 +       }
 265 +
 266 +       if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
 267 +               /* TODO: flush DDR? */
 268 +               generic_handle_irq(ATH79_IP3_IRQ(2));
 269 +       }
 270 +}
 271 +
 272 +static void qca956x_enable_timer_cb(void) {
 273 +       u32 misc;
 274 +
 275 +       misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 276 +       misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
 277 +       ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
 278 +}
 279 +
 280 +static void qca956x_irq_init(void)
 281 +{
 282 +       int i;
 283 +
 284 +       for (i = ATH79_IP2_IRQ_BASE;
 285 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 286 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 287 +
 288 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 289 +
 290 +       for (i = ATH79_IP3_IRQ_BASE;
 291 +            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 292 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 293 +
 294 +       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 295 +
 296 +       /* QCA956x timer init workaround has to be applied right before setting
 297 +        * up the clock. Else, there will be no jiffies */
 298 +       late_time_init = &qca956x_enable_timer_cb;
 299 +}
 300 +
 301  void __init arch_init_irq(void)
 302  {
 303         unsigned irq_wb_chan2 = -1;
 304 @@ -183,7 +264,9 @@ void __init arch_init_irq(void)
 305                  soc_is_ar933x() ||
 306                  soc_is_ar934x() ||
 307                  soc_is_qca953x() ||
 308 -                soc_is_qca955x())
 309 +                soc_is_qca955x() ||
 310 +                soc_is_qca956x() ||
 311 +                soc_is_tp9343())
 312                 misc_is_ar71xx = false;
 313         else
 314                 BUG();
 315 @@ -197,4 +280,6 @@ void __init arch_init_irq(void)
 316                 qca953x_irq_init();
 317         else if (soc_is_qca955x())
 318                 qca955x_irq_init();
 319 +       else if (soc_is_qca956x() || soc_is_tp9343())
 320 +               qca956x_irq_init();
 321  }
 322 diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c
 323 index b816cb4a25ff..d905a67e1a07 100644
 324 --- a/arch/mips/ath79/pci.c
 325 +++ b/arch/mips/ath79/pci.c
 326 @@ -82,6 +82,9 @@ int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
 327                 } else if (soc_is_qca955x()) {
 328                         ath79_pci_irq_map = qca955x_pci_irq_map;
 329                         ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
 330 +               } else if (soc_is_qca956x()) {
 331 +                       ath79_pci_irq_map = qca956x_pci_irq_map;
 332 +                       ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
 333                 } else {
 334                         pr_crit("pci %s: invalid irq map\n",
 335                                 pci_name((struct pci_dev *) dev));
 336 @@ -261,6 +264,15 @@ int __init ath79_register_pci(void)
 337                                                  QCA955X_PCI_MEM_SIZE,
 338                                                  1,
 339                                                  ATH79_IP3_IRQ(2));
 340 +       } else if (soc_is_qca956x()) {
 341 +               pdev = ath79_register_pci_ar724x(0,
 342 +                                                QCA956X_PCI_CFG_BASE1,
 343 +                                                QCA956X_PCI_CTRL_BASE1,
 344 +                                                QCA956X_PCI_CRP_BASE1,
 345 +                                                QCA956X_PCI_MEM_BASE1,
 346 +                                                QCA956X_PCI_MEM_SIZE,
 347 +                                                1,
 348 +                                                ATH79_IP3_IRQ(2));
 349         } else {
 350                 /* No PCI support */
 351                 return -ENODEV;
 352 diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
 353 index f782ae6c77d6..4c7a93f4039a 100644
 354 --- a/arch/mips/ath79/setup.c
 355 +++ b/arch/mips/ath79/setup.c
 356 @@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type(void)
 357                 rev = id & QCA955X_REV_ID_REVISION_MASK;
 358                 break;
 359
 360 +       case REV_ID_MAJOR_QCA956X:
 361 +               ath79_soc = ATH79_SOC_QCA956X;
 362 +               chip = "956X";
 363 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 364 +               break;
 365 +
 366 +       case REV_ID_MAJOR_TP9343:
 367 +               ath79_soc = ATH79_SOC_TP9343;
 368 +               chip = "9343";
 369 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 370 +               break;
 371 +
 372         default:
 373                 panic("ath79: unknown SoC, id:0x%08x", id);
 374         }
 375 @@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type(void)
 376         if (ver == 1)
 377                 ath79_soc_rev = rev;
 378
 379 -       if (soc_is_qca953x() || soc_is_qca955x())
 380 +       if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
 381                 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 382                         chip, ver, rev);
 383 +       else if (soc_is_tp9343())
 384 +               sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
 385 +                       chip, rev);
 386         else
 387                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 388         pr_info("SoC: %s\n", ath79_sys_type);
 389 diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
 390 index 98a7ccf3d358..73dcd63b8243 100644
 391 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 392 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 393 @@ -35,6 +35,8 @@ enum ath79_soc_type {
 394         ATH79_SOC_QCA9533,
 395         ATH79_SOC_QCA9556,
 396         ATH79_SOC_QCA9558,
 397 +       ATH79_SOC_TP9343,
 398 +       ATH79_SOC_QCA956X,
 399  };
 400
 401  extern enum ath79_soc_type ath79_soc;
 402 @@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
 403         return soc_is_qca9556() || soc_is_qca9558();
 404  }
 405
 406 +static inline int soc_is_tp9343(void)
 407 +{
 408 +       return ath79_soc == ATH79_SOC_TP9343;
 409 +}
 410 +
 411 +static inline int soc_is_qca9561(void)
 412 +{
 413 +       return ath79_soc == ATH79_SOC_QCA956X;
 414 +}
 415 +
 416 +static inline int soc_is_qca9563(void)
 417 +{
 418 +       return ath79_soc == ATH79_SOC_QCA956X;
 419 +}
 420 +
 421 +static inline int soc_is_qca956x(void)
 422 +{
 423 +       return soc_is_qca9561() || soc_is_qca9563();
 424 +}
 425 +
 426  void ath79_ddr_wb_flush(unsigned int reg);
 427  void ath79_ddr_set_pci_windows(void);
 428
 429 --
 430 2.11.0
 431