target/linux/ath79/patches-4.14/0016-MIPS-ath79-add-support-for-QCA953x-SoC.patch

   1 From cff23ba486e3c5d17c4d7e446f5eddead855c101 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 6 Mar 2018 08:45:55 +0100
   4 Subject: [PATCH 16/27] MIPS: ath79: add support for QCA953x SoC
   5
   6 Note that the clock calculation looks very similar to the QCA955x, but the
   7 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
   8
   9 Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
  10 ---
  11  arch/mips/ath79/Kconfig                  |  6 ++-
  12  arch/mips/ath79/clock.c                  | 87 ++++++++++++++++++++++++++++++++
  13  arch/mips/ath79/common.c                 |  4 ++
  14  arch/mips/ath79/dev-common.c             |  4 ++
  15  arch/mips/ath79/early_printk.c           |  2 +
  16  arch/mips/ath79/irq.c                    | 33 +++++++++++-
  17  arch/mips/ath79/setup.c                  | 21 ++++++--
  18  arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
  19  8 files changed, 162 insertions(+), 6 deletions(-)
  20
  21 --- a/arch/mips/ath79/Kconfig
  22 +++ b/arch/mips/ath79/Kconfig
  23 @@ -94,6 +94,10 @@ config SOC_AR934X
  24         select PCI_AR724X if PCI
  25         def_bool n
  26
  27 +config SOC_QCA953X
  28 +       select USB_ARCH_HAS_EHCI
  29 +       def_bool n
  30 +
  31  config SOC_QCA955X
  32         select HW_HAS_PCI
  33         select PCI_AR724X if PCI
  34 @@ -115,7 +119,7 @@ config ATH79_DEV_USB
  35         def_bool n
  36
  37  config ATH79_DEV_WMAC
  38 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  39 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  40         def_bool n
  41
  42  endif
  43 --- a/arch/mips/ath79/clock.c
  44 +++ b/arch/mips/ath79/clock.c
  45 @@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo
  46         iounmap(dpll_base);
  47  }
  48
  49 +static void __init qca953x_clocks_init(void)
  50 +{
  51 +       unsigned long ref_rate;
  52 +       unsigned long cpu_rate;
  53 +       unsigned long ddr_rate;
  54 +       unsigned long ahb_rate;
  55 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  56 +       u32 cpu_pll, ddr_pll;
  57 +       u32 bootstrap;
  58 +
  59 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  60 +       if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  61 +               ref_rate = 40 * 1000 * 1000;
  62 +       else
  63 +               ref_rate = 25 * 1000 * 1000;
  64 +
  65 +       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  66 +       out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  67 +                 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  68 +       ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  69 +                 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  70 +       nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  71 +              QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  72 +       frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  73 +              QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  74 +
  75 +       cpu_pll = nint * ref_rate / ref_div;
  76 +       cpu_pll += frac * (ref_rate >> 6) / ref_div;
  77 +       cpu_pll /= (1 << out_div);
  78 +
  79 +       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  80 +       out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  81 +                 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  82 +       ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  83 +                 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  84 +       nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  85 +              QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  86 +       frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  87 +              QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  88 +
  89 +       ddr_pll = nint * ref_rate / ref_div;
  90 +       ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
  91 +       ddr_pll /= (1 << out_div);
  92 +
  93 +       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  94 +
  95 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  96 +                 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  97 +
  98 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  99 +               cpu_rate = ref_rate;
 100 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 101 +               cpu_rate = cpu_pll / (postdiv + 1);
 102 +       else
 103 +               cpu_rate = ddr_pll / (postdiv + 1);
 104 +
 105 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 106 +                 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 107 +
 108 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 109 +               ddr_rate = ref_rate;
 110 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 111 +               ddr_rate = ddr_pll / (postdiv + 1);
 112 +       else
 113 +               ddr_rate = cpu_pll / (postdiv + 1);
 114 +
 115 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 116 +                 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 117 +
 118 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 119 +               ahb_rate = ref_rate;
 120 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 121 +               ahb_rate = ddr_pll / (postdiv + 1);
 122 +       else
 123 +               ahb_rate = cpu_pll / (postdiv + 1);
 124 +
 125 +       ath79_add_sys_clkdev("ref", ref_rate);
 126 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 127 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 128 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 129 +
 130 +       clk_add_alias("wdt", NULL, "ref", NULL);
 131 +       clk_add_alias("uart", NULL, "ref", NULL);
 132 +}
 133 +
 134  static void __init qca955x_clocks_init(void)
 135  {
 136         unsigned long ref_rate;
 137 @@ -450,6 +535,8 @@ void __init ath79_clocks_init(void)
 138                 ar933x_clocks_init();
 139         else if (soc_is_ar934x())
 140                 ar934x_clocks_init();
 141 +       else if (soc_is_qca953x())
 142 +               qca953x_clocks_init();
 143         else if (soc_is_qca955x())
 144                 qca955x_clocks_init();
 145         else
 146 --- a/arch/mips/ath79/common.c
 147 +++ b/arch/mips/ath79/common.c
 148 @@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
 149                 reg = AR933X_RESET_REG_RESET_MODULE;
 150         else if (soc_is_ar934x())
 151                 reg = AR934X_RESET_REG_RESET_MODULE;
 152 +       else if (soc_is_qca953x())
 153 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 154         else if (soc_is_qca955x())
 155                 reg = QCA955X_RESET_REG_RESET_MODULE;
 156         else
 157 @@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
 158                 reg = AR933X_RESET_REG_RESET_MODULE;
 159         else if (soc_is_ar934x())
 160                 reg = AR934X_RESET_REG_RESET_MODULE;
 161 +       else if (soc_is_qca953x())
 162 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 163         else if (soc_is_qca955x())
 164                 reg = QCA955X_RESET_REG_RESET_MODULE;
 165         else
 166 --- a/arch/mips/ath79/dev-common.c
 167 +++ b/arch/mips/ath79/dev-common.c
 168 @@ -85,6 +85,7 @@ void __init ath79_register_uart(void)
 169             soc_is_ar724x() ||
 170             soc_is_ar913x() ||
 171             soc_is_ar934x() ||
 172 +           soc_is_qca953x() ||
 173             soc_is_qca955x()) {
 174                 ath79_uart_data[0].uartclk = uart_clk_rate;
 175                 platform_device_register(&ath79_uart_device);
 176 @@ -148,6 +149,9 @@ void __init ath79_gpio_init(void)
 177         } else if (soc_is_ar934x()) {
 178                 ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
 179                 ath79_gpio_pdata.oe_inverted = 1;
 180 +       } else if (soc_is_qca953x()) {
 181 +               ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
 182 +               ath79_gpio_pdata.oe_inverted = 1;
 183         } else if (soc_is_qca955x()) {
 184                 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
 185                 ath79_gpio_pdata.oe_inverted = 1;
 186 --- a/arch/mips/ath79/early_printk.c
 187 +++ b/arch/mips/ath79/early_printk.c
 188 @@ -116,6 +116,8 @@ static void prom_putchar_init(void)
 189         case REV_ID_MAJOR_AR9341:
 190         case REV_ID_MAJOR_AR9342:
 191         case REV_ID_MAJOR_AR9344:
 192 +       case REV_ID_MAJOR_QCA9533:
 193 +       case REV_ID_MAJOR_QCA9533_V2:
 194         case REV_ID_MAJOR_QCA9556:
 195         case REV_ID_MAJOR_QCA9558:
 196                 _prom_putchar = prom_putchar_ar71xx;
 197 --- a/arch/mips/ath79/irq.c
 198 +++ b/arch/mips/ath79/irq.c
 199 @@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void)
 200         irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
 201  }
 202
 203 +static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
 204 +{
 205 +       u32 status;
 206 +
 207 +       status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
 208 +
 209 +       if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
 210 +               ath79_ddr_wb_flush(3);
 211 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 212 +       } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
 213 +               ath79_ddr_wb_flush(4);
 214 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 215 +       } else {
 216 +               spurious_interrupt();
 217 +       }
 218 +}
 219 +
 220 +static void qca953x_irq_init(void)
 221 +{
 222 +       int i;
 223 +
 224 +       for (i = ATH79_IP2_IRQ_BASE;
 225 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 226 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 227 +
 228 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
 229 +}
 230 +
 231  static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
 232  {
 233         u32 status;
 234 @@ -143,7 +171,7 @@ void __init arch_init_irq(void)
 235             soc_is_ar913x() || soc_is_ar933x()) {
 236                 irq_wb_chan2 = 3;
 237                 irq_wb_chan3 = 2;
 238 -       } else if (soc_is_ar934x()) {
 239 +       } else if (soc_is_ar934x() || soc_is_qca953x()) {
 240                 irq_wb_chan3 = 2;
 241         }
 242
 243 @@ -154,6 +182,7 @@ void __init arch_init_irq(void)
 244         else if (soc_is_ar724x() ||
 245                  soc_is_ar933x() ||
 246                  soc_is_ar934x() ||
 247 +                soc_is_qca953x() ||
 248                  soc_is_qca955x())
 249                 misc_is_ar71xx = false;
 250         else
 251 @@ -164,6 +193,8 @@ void __init arch_init_irq(void)
 252
 253         if (soc_is_ar934x())
 254                 ar934x_ip2_irq_init();
 255 +       else if (soc_is_qca953x())
 256 +               qca953x_irq_init();
 257         else if (soc_is_qca955x())
 258                 qca955x_irq_init();
 259  }
 260 --- a/arch/mips/ath79/setup.c
 261 +++ b/arch/mips/ath79/setup.c
 262 @@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
 263         u32 major;
 264         u32 minor;
 265         u32 rev = 0;
 266 +       u32 ver = 1;
 267
 268         id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
 269         major = id & REV_ID_MAJOR_MASK;
 270 @@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
 271                 rev = id & AR934X_REV_ID_REVISION_MASK;
 272                 break;
 273
 274 +       case REV_ID_MAJOR_QCA9533_V2:
 275 +               ver = 2;
 276 +               ath79_soc_rev = 2;
 277 +               /* drop through */
 278 +
 279 +       case REV_ID_MAJOR_QCA9533:
 280 +               ath79_soc = ATH79_SOC_QCA9533;
 281 +               chip = "9533";
 282 +               rev = id & QCA953X_REV_ID_REVISION_MASK;
 283 +               break;
 284 +
 285         case REV_ID_MAJOR_QCA9556:
 286                 ath79_soc = ATH79_SOC_QCA9556;
 287                 chip = "9556";
 288 @@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type
 289                 panic("ath79: unknown SoC, id:0x%08x", id);
 290         }
 291
 292 -       ath79_soc_rev = rev;
 293 +       if (ver == 1)
 294 +               ath79_soc_rev = rev;
 295
 296 -       if (soc_is_qca955x())
 297 -               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 298 -                       chip, rev);
 299 +       if (soc_is_qca953x() || soc_is_qca955x())
 300 +               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 301 +                       chip, ver, rev);
 302         else
 303                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 304         pr_info("SoC: %s\n", ath79_sys_type);
 305 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 306 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 307 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 308         ATH79_SOC_AR9341,
 309         ATH79_SOC_AR9342,
 310         ATH79_SOC_AR9344,
 311 +       ATH79_SOC_QCA9533,
 312         ATH79_SOC_QCA9556,
 313         ATH79_SOC_QCA9558,
 314  };
 315 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
 316         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 317  }
 318
 319 +static inline int soc_is_qca9533(void)
 320 +{
 321 +       return ath79_soc == ATH79_SOC_QCA9533;
 322 +}
 323 +
 324 +static inline int soc_is_qca953x(void)
 325 +{
 326 +       return soc_is_qca9533();
 327 +}
 328 +
 329  static inline int soc_is_qca9556(void)
 330  {
 331         return ath79_soc == ATH79_SOC_QCA9556;