1 From 3ea2bff4ed3ce74dc4303aa20f5e906e78352f6b Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 6 Mar 2018 10:06:10 +0100
4 Subject: [PATCH 09/27] MIPS: ath79: add lots of missing registers
6 Signed-off-by: John Crispin <john@phrozen.org>
8 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 773 ++++++++++++++++++++++++-
9 1 file changed, 771 insertions(+), 2 deletions(-)
11 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
12 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
14 #include <linux/bitops.h>
16 #define AR71XX_APB_BASE 0x18000000
17 +#define AR71XX_GE0_BASE 0x19000000
18 +#define AR71XX_GE0_SIZE 0x10000
19 +#define AR71XX_GE1_BASE 0x1a000000
20 +#define AR71XX_GE1_SIZE 0x10000
21 #define AR71XX_EHCI_BASE 0x1b000000
22 #define AR71XX_EHCI_SIZE 0x1000
23 #define AR71XX_OHCI_BASE 0x1c000000
25 #define AR71XX_PLL_SIZE 0x100
26 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
27 #define AR71XX_RESET_SIZE 0x100
28 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
29 +#define AR71XX_MII_SIZE 0x100
31 #define AR71XX_PCI_MEM_BASE 0x10000000
32 #define AR71XX_PCI_MEM_SIZE 0x07000000
35 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
36 #define AR933X_UART_SIZE 0x14
37 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
38 +#define AR933X_GMAC_SIZE 0x04
39 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
40 #define AR933X_WMAC_SIZE 0x20000
41 #define AR933X_EHCI_BASE 0x1b000000
42 #define AR933X_EHCI_SIZE 0x1000
44 +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
45 +#define AR934X_GMAC_SIZE 0x14
46 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
47 #define AR934X_WMAC_SIZE 0x20000
48 #define AR934X_EHCI_BASE 0x1b000000
49 #define AR934X_EHCI_SIZE 0x200
50 +#define AR934X_NFC_BASE 0x1b000200
51 +#define AR934X_NFC_SIZE 0xb8
52 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
53 #define AR934X_SRIF_SIZE 0x1000
55 +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
56 +#define QCA953X_GMAC_SIZE 0x14
57 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
58 +#define QCA953X_WMAC_SIZE 0x20000
59 +#define QCA953X_EHCI_BASE 0x1b000000
60 +#define QCA953X_EHCI_SIZE 0x200
61 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
62 +#define QCA953X_SRIF_SIZE 0x1000
64 +#define QCA953X_PCI_CFG_BASE0 0x14000000
65 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
66 +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
67 +#define QCA953X_PCI_MEM_BASE0 0x10000000
68 +#define QCA953X_PCI_MEM_SIZE 0x02000000
70 #define QCA955X_PCI_MEM_BASE0 0x10000000
71 #define QCA955X_PCI_MEM_BASE1 0x12000000
72 #define QCA955X_PCI_MEM_SIZE 0x02000000
74 #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
75 #define QCA955X_PCI_CTRL_SIZE 0x100
77 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
78 +#define QCA955X_GMAC_SIZE 0x40
79 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
80 #define QCA955X_WMAC_SIZE 0x20000
81 #define QCA955X_EHCI0_BASE 0x1b000000
82 #define QCA955X_EHCI1_BASE 0x1b400000
83 #define QCA955X_EHCI_SIZE 0x1000
84 +#define QCA955X_NFC_BASE 0x1b800200
85 +#define QCA955X_NFC_SIZE 0xb8
87 +#define QCA956X_PCI_MEM_BASE1 0x12000000
88 +#define QCA956X_PCI_MEM_SIZE 0x02000000
89 +#define QCA956X_PCI_CFG_BASE1 0x16000000
90 +#define QCA956X_PCI_CFG_SIZE 0x1000
91 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
92 +#define QCA956X_PCI_CRP_SIZE 0x1000
93 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
94 +#define QCA956X_PCI_CTRL_SIZE 0x100
96 +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
97 +#define QCA956X_WMAC_SIZE 0x20000
98 +#define QCA956X_EHCI0_BASE 0x1b000000
99 +#define QCA956X_EHCI1_BASE 0x1b400000
100 +#define QCA956X_EHCI_SIZE 0x200
101 +#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
102 +#define QCA956X_GMAC_SGMII_SIZE 0x64
103 +#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
104 +#define QCA956X_PLL_SIZE 0x50
105 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
106 +#define QCA956X_GMAC_SIZE 0x64
111 +#define QCA956X_MAC_CFG_BASE 0xb9000000
112 +#define QCA956X_MAC_CFG_SIZE 0x64
114 +#define QCA956X_MAC_CFG1_REG 0x00
115 +#define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
116 +#define QCA956X_MAC_CFG1_RX_RST BIT(19)
117 +#define QCA956X_MAC_CFG1_TX_RST BIT(18)
118 +#define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
119 +#define QCA956X_MAC_CFG1_RX_EN BIT(2)
120 +#define QCA956X_MAC_CFG1_TX_EN BIT(0)
122 +#define QCA956X_MAC_CFG2_REG 0x04
123 +#define QCA956X_MAC_CFG2_IF_1000 BIT(9)
124 +#define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
125 +#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
126 +#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
127 +#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
128 +#define QCA956X_MAC_CFG2_FDX BIT(0)
130 +#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
131 +#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
133 +#define QCA956X_MAC_FIFO_CFG0_REG 0x48
134 +#define QCA956X_MAC_FIFO_CFG1_REG 0x4c
135 +#define QCA956X_MAC_FIFO_CFG2_REG 0x50
136 +#define QCA956X_MAC_FIFO_CFG3_REG 0x54
137 +#define QCA956X_MAC_FIFO_CFG4_REG 0x58
138 +#define QCA956X_MAC_FIFO_CFG5_REG 0x5c
140 +#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
141 +#define QCA956X_DAM_RESET_SIZE 0x4
142 +#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
147 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
148 #define AR934X_DDR_REG_FLUSH_WMAC 0xac
150 +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
151 +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
152 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4
153 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
154 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
160 #define AR71XX_AHB_DIV_SHIFT 20
161 #define AR71XX_AHB_DIV_MASK 0x7
163 +#define AR71XX_ETH0_PLL_SHIFT 17
164 +#define AR71XX_ETH1_PLL_SHIFT 19
166 #define AR724X_PLL_REG_CPU_CONFIG 0x00
167 #define AR724X_PLL_REG_PCIE_CONFIG 0x10
169 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
170 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
172 #define AR724X_PLL_FB_SHIFT 0
173 #define AR724X_PLL_FB_MASK 0x3ff
174 #define AR724X_PLL_REF_DIV_SHIFT 10
176 #define AR724X_DDR_DIV_SHIFT 22
177 #define AR724X_DDR_DIV_MASK 0x3
179 +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
181 #define AR913X_PLL_REG_CPU_CONFIG 0x00
182 #define AR913X_PLL_REG_ETH_CONFIG 0x04
183 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
185 #define AR913X_AHB_DIV_SHIFT 19
186 #define AR913X_AHB_DIV_MASK 0x1
188 +#define AR913X_ETH0_PLL_SHIFT 20
189 +#define AR913X_ETH1_PLL_SHIFT 22
191 #define AR933X_PLL_CPU_CONFIG_REG 0x00
192 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
195 #define AR934X_PLL_CPU_CONFIG_REG 0x00
196 #define AR934X_PLL_DDR_CONFIG_REG 0x04
197 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
198 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
199 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
201 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
202 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
204 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
205 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
207 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
209 +#define QCA953X_PLL_CPU_CONFIG_REG 0x00
210 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04
211 +#define QCA953X_PLL_CLK_CTRL_REG 0x08
212 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
213 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
214 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
216 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
217 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
218 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
219 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
220 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
221 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
222 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
223 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
225 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
226 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
227 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
228 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
229 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
230 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
231 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
232 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
234 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
235 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
236 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
237 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
238 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
239 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
240 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
241 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
242 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
243 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
244 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
245 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
247 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
248 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
249 #define QCA955X_PLL_CLK_CTRL_REG 0x08
250 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
251 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
252 +#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
254 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
255 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
257 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
258 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
260 +#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
261 +#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
262 +#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
264 +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
265 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
266 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
267 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
268 +#define QCA956X_PLL_CLK_CTRL_REG 0x10
269 +#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
270 +#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
271 +#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
273 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
274 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
275 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
276 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
278 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
279 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
280 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
281 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
282 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
283 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
285 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
286 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
287 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
288 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
290 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
291 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
292 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
293 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
294 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
295 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
297 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
298 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
299 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
300 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
301 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
302 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
303 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
304 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
305 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
306 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
307 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
308 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
310 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
311 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
312 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
313 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
314 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
315 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
316 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
317 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
318 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
319 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
320 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
321 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
322 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
324 +#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
325 +#define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
326 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28
327 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
328 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26
329 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3
331 +#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
332 +#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
333 +#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
338 @@ -317,10 +542,19 @@
339 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
340 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
342 +#define QCA953X_RESET_REG_RESET_MODULE 0x1c
343 +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
344 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
346 #define QCA955X_RESET_REG_RESET_MODULE 0x1c
347 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
348 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
350 +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
351 +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
352 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
354 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
355 #define MISC_INT_ETHSW BIT(12)
356 #define MISC_INT_TIMER4 BIT(10)
357 #define MISC_INT_TIMER3 BIT(9)
358 @@ -370,16 +604,123 @@
359 #define AR913X_RESET_USB_HOST BIT(5)
360 #define AR913X_RESET_USB_PHY BIT(4)
362 +#define AR933X_RESET_GE1_MDIO BIT(23)
363 +#define AR933X_RESET_GE0_MDIO BIT(22)
364 +#define AR933X_RESET_GE1_MAC BIT(13)
365 #define AR933X_RESET_WMAC BIT(11)
366 +#define AR933X_RESET_GE0_MAC BIT(9)
367 #define AR933X_RESET_USB_HOST BIT(5)
368 #define AR933X_RESET_USB_PHY BIT(4)
369 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
371 +#define AR934X_RESET_HOST BIT(31)
372 +#define AR934X_RESET_SLIC BIT(30)
373 +#define AR934X_RESET_HDMA BIT(29)
374 +#define AR934X_RESET_EXTERNAL BIT(28)
375 +#define AR934X_RESET_RTC BIT(27)
376 +#define AR934X_RESET_PCIE_EP_INT BIT(26)
377 +#define AR934X_RESET_CHKSUM_ACC BIT(25)
378 +#define AR934X_RESET_FULL_CHIP BIT(24)
379 +#define AR934X_RESET_GE1_MDIO BIT(23)
380 +#define AR934X_RESET_GE0_MDIO BIT(22)
381 +#define AR934X_RESET_CPU_NMI BIT(21)
382 +#define AR934X_RESET_CPU_COLD BIT(20)
383 +#define AR934X_RESET_HOST_RESET_INT BIT(19)
384 +#define AR934X_RESET_PCIE_EP BIT(18)
385 +#define AR934X_RESET_UART1 BIT(17)
386 +#define AR934X_RESET_DDR BIT(16)
387 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
388 +#define AR934X_RESET_NANDF BIT(14)
389 +#define AR934X_RESET_GE1_MAC BIT(13)
390 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
391 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
392 +#define AR934X_RESET_HOST_DMA_INT BIT(10)
393 +#define AR934X_RESET_GE0_MAC BIT(9)
394 +#define AR934X_RESET_ETH_SWITCH BIT(8)
395 +#define AR934X_RESET_PCIE_PHY BIT(7)
396 +#define AR934X_RESET_PCIE BIT(6)
397 #define AR934X_RESET_USB_HOST BIT(5)
398 #define AR934X_RESET_USB_PHY BIT(4)
399 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
400 +#define AR934X_RESET_LUT BIT(2)
401 +#define AR934X_RESET_MBOX BIT(1)
402 +#define AR934X_RESET_I2S BIT(0)
404 +#define QCA953X_RESET_USB_EXT_PWR BIT(29)
405 +#define QCA953X_RESET_EXTERNAL BIT(28)
406 +#define QCA953X_RESET_RTC BIT(27)
407 +#define QCA953X_RESET_FULL_CHIP BIT(24)
408 +#define QCA953X_RESET_GE1_MDIO BIT(23)
409 +#define QCA953X_RESET_GE0_MDIO BIT(22)
410 +#define QCA953X_RESET_CPU_NMI BIT(21)
411 +#define QCA953X_RESET_CPU_COLD BIT(20)
412 +#define QCA953X_RESET_DDR BIT(16)
413 +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
414 +#define QCA953X_RESET_GE1_MAC BIT(13)
415 +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
416 +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
417 +#define QCA953X_RESET_GE0_MAC BIT(9)
418 +#define QCA953X_RESET_ETH_SWITCH BIT(8)
419 +#define QCA953X_RESET_PCIE_PHY BIT(7)
420 +#define QCA953X_RESET_PCIE BIT(6)
421 +#define QCA953X_RESET_USB_HOST BIT(5)
422 +#define QCA953X_RESET_USB_PHY BIT(4)
423 +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
425 +#define QCA955X_RESET_HOST BIT(31)
426 +#define QCA955X_RESET_SLIC BIT(30)
427 +#define QCA955X_RESET_HDMA BIT(29)
428 +#define QCA955X_RESET_EXTERNAL BIT(28)
429 +#define QCA955X_RESET_RTC BIT(27)
430 +#define QCA955X_RESET_PCIE_EP_INT BIT(26)
431 +#define QCA955X_RESET_CHKSUM_ACC BIT(25)
432 +#define QCA955X_RESET_FULL_CHIP BIT(24)
433 +#define QCA955X_RESET_GE1_MDIO BIT(23)
434 +#define QCA955X_RESET_GE0_MDIO BIT(22)
435 +#define QCA955X_RESET_CPU_NMI BIT(21)
436 +#define QCA955X_RESET_CPU_COLD BIT(20)
437 +#define QCA955X_RESET_HOST_RESET_INT BIT(19)
438 +#define QCA955X_RESET_PCIE_EP BIT(18)
439 +#define QCA955X_RESET_UART1 BIT(17)
440 +#define QCA955X_RESET_DDR BIT(16)
441 +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
442 +#define QCA955X_RESET_NANDF BIT(14)
443 +#define QCA955X_RESET_GE1_MAC BIT(13)
444 +#define QCA955X_RESET_SGMII_ANALOG BIT(12)
445 +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
446 +#define QCA955X_RESET_HOST_DMA_INT BIT(10)
447 +#define QCA955X_RESET_GE0_MAC BIT(9)
448 +#define QCA955X_RESET_SGMII BIT(8)
449 +#define QCA955X_RESET_PCIE_PHY BIT(7)
450 +#define QCA955X_RESET_PCIE BIT(6)
451 +#define QCA955X_RESET_USB_HOST BIT(5)
452 +#define QCA955X_RESET_USB_PHY BIT(4)
453 +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
454 +#define QCA955X_RESET_LUT BIT(2)
455 +#define QCA955X_RESET_MBOX BIT(1)
456 +#define QCA955X_RESET_I2S BIT(0)
458 +#define QCA956X_RESET_EXTERNAL BIT(28)
459 +#define QCA956X_RESET_FULL_CHIP BIT(24)
460 +#define QCA956X_RESET_GE1_MDIO BIT(23)
461 +#define QCA956X_RESET_GE0_MDIO BIT(22)
462 +#define QCA956X_RESET_CPU_NMI BIT(21)
463 +#define QCA956X_RESET_CPU_COLD BIT(20)
464 +#define QCA956X_RESET_DMA BIT(19)
465 +#define QCA956X_RESET_DDR BIT(16)
466 +#define QCA956X_RESET_GE1_MAC BIT(13)
467 +#define QCA956X_RESET_SGMII_ANALOG BIT(12)
468 +#define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
469 +#define QCA956X_RESET_GE0_MAC BIT(9)
470 +#define QCA956X_RESET_SGMII BIT(8)
471 +#define QCA956X_RESET_USB_HOST BIT(5)
472 +#define QCA956X_RESET_USB_PHY BIT(4)
473 +#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
474 +#define QCA956X_RESET_SWITCH_ANALOG BIT(2)
475 +#define QCA956X_RESET_SWITCH BIT(0)
477 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
478 +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
479 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
481 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
483 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
484 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
486 +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
487 +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
488 +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
489 +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
490 +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
491 +#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
493 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
495 +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
497 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
498 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
499 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
501 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
502 AR934X_PCIE_WMAC_INT_PCIE_RC3)
504 +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
505 +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
506 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
507 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
508 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
509 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
510 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
511 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
512 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
513 +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
514 + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
515 + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
517 +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
518 + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
519 + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
520 + QCA953X_PCIE_WMAC_INT_PCIE_RC3)
522 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
523 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
524 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
526 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
527 QCA955X_EXT_INT_PCIE_RC2_INT3)
529 +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
530 +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
531 +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
532 +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
533 +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
534 +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
535 +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
536 +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
537 +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
538 +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
539 +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
540 +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
541 +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
542 +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
543 +#define QCA956X_EXT_INT_USB1 BIT(24)
544 +#define QCA956X_EXT_INT_USB2 BIT(28)
546 +#define QCA956X_EXT_INT_WMAC_ALL \
547 + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
548 + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
550 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
551 + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
552 + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
553 + QCA956X_EXT_INT_PCIE_RC1_INT3)
555 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
556 + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
557 + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
558 + QCA956X_EXT_INT_PCIE_RC2_INT3)
560 #define REV_ID_MAJOR_MASK 0xfff0
561 #define REV_ID_MAJOR_AR71XX 0x00a0
562 #define REV_ID_MAJOR_AR913X 0x00b0
564 #define REV_ID_MAJOR_AR9341 0x0120
565 #define REV_ID_MAJOR_AR9342 0x1120
566 #define REV_ID_MAJOR_AR9344 0x2120
567 +#define REV_ID_MAJOR_QCA9533 0x0140
568 +#define REV_ID_MAJOR_QCA9533_V2 0x0160
569 #define REV_ID_MAJOR_QCA9556 0x0130
570 #define REV_ID_MAJOR_QCA9558 0x1130
571 +#define REV_ID_MAJOR_TP9343 0x0150
572 +#define REV_ID_MAJOR_QCA956X 0x1150
574 #define AR71XX_REV_ID_MINOR_MASK 0x3
575 #define AR71XX_REV_ID_MINOR_AR7130 0x0
578 #define AR934X_REV_ID_REVISION_MASK 0xf
580 +#define QCA953X_REV_ID_REVISION_MASK 0xf
582 #define QCA955X_REV_ID_REVISION_MASK 0xf
584 +#define QCA956X_REV_ID_REVISION_MASK 0xf
589 @@ -521,15 +928,63 @@
590 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
591 #define AR71XX_GPIO_REG_FUNC 0x28
593 +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
594 +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
595 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
596 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
597 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
598 +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
599 #define AR934X_GPIO_REG_FUNC 0x6c
601 +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
602 +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
603 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
604 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
605 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
606 +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
607 +#define QCA953X_GPIO_REG_FUNC 0x6c
609 +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
610 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
611 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
612 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
613 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
614 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
615 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
616 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
617 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
618 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
620 +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
621 +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
622 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
623 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
624 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
625 +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
626 +#define QCA955X_GPIO_REG_FUNC 0x6c
628 +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
629 +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
630 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
631 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
632 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
633 +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
634 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
635 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
636 +#define QCA956X_GPIO_REG_FUNC 0x6c
638 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
639 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
641 #define AR71XX_GPIO_COUNT 16
642 #define AR7240_GPIO_COUNT 18
643 #define AR7241_GPIO_COUNT 20
644 #define AR913X_GPIO_COUNT 22
645 #define AR933X_GPIO_COUNT 30
646 #define AR934X_GPIO_COUNT 23
647 +#define QCA953X_GPIO_COUNT 18
648 #define QCA955X_GPIO_COUNT 24
649 +#define QCA956X_GPIO_COUNT 23
653 @@ -552,4 +1007,318 @@
654 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
655 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
657 +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
658 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
659 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
661 +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
662 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
663 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
665 +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
666 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
667 +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
668 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
669 +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
671 +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
672 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
673 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
675 +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
676 +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
677 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
678 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
679 +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
680 +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
681 +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
683 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
684 +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
685 +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
686 +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
687 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
688 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
689 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
690 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
691 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
692 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
693 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
694 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
695 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
696 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
697 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
698 +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
699 +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
701 +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
702 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
703 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
704 +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
705 +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
706 +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
707 +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
708 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
709 +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
710 +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
712 +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
713 +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
714 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
715 +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
716 +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
717 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
718 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
719 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
720 +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
721 +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
722 +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
723 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
724 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
725 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
726 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
727 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
728 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
729 +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
730 +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
732 +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
733 +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
734 +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
735 +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
736 +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
737 +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
738 +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
739 +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
740 +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
742 +#define AR934X_GPIO_OUT_GPIO 0
743 +#define AR934X_GPIO_OUT_SPI_CS1 7
744 +#define AR934X_GPIO_OUT_LED_LINK0 41
745 +#define AR934X_GPIO_OUT_LED_LINK1 42
746 +#define AR934X_GPIO_OUT_LED_LINK2 43
747 +#define AR934X_GPIO_OUT_LED_LINK3 44
748 +#define AR934X_GPIO_OUT_LED_LINK4 45
749 +#define AR934X_GPIO_OUT_EXT_LNA0 46
750 +#define AR934X_GPIO_OUT_EXT_LNA1 47
752 +#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
753 +#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
754 +#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
755 +#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
756 +#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
757 +#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
758 +#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
759 +#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
761 +#define QCA955X_GPIO_OUT_GPIO 0
762 +#define QCA955X_MII_EXT_MDI 1
763 +#define QCA955X_SLIC_DATA_OUT 3
764 +#define QCA955X_SLIC_PCM_FS 4
765 +#define QCA955X_SLIC_PCM_CLK 5
766 +#define QCA955X_SPI_CLK 8
767 +#define QCA955X_SPI_CS_0 9
768 +#define QCA955X_SPI_CS_1 10
769 +#define QCA955X_SPI_CS_2 11
770 +#define QCA955X_SPI_MISO 12
771 +#define QCA955X_I2S_CLK 13
772 +#define QCA955X_I2S_WS 14
773 +#define QCA955X_I2S_SD 15
774 +#define QCA955X_I2S_MCK 16
775 +#define QCA955X_SPDIF_OUT 17
776 +#define QCA955X_UART1_TD 18
777 +#define QCA955X_UART1_RTS 19
778 +#define QCA955X_UART1_RD 20
779 +#define QCA955X_UART1_CTS 21
780 +#define QCA955X_UART0_SOUT 22
781 +#define QCA955X_SPDIF2_OUT 23
782 +#define QCA955X_LED_SGMII_SPEED0 24
783 +#define QCA955X_LED_SGMII_SPEED1 25
784 +#define QCA955X_LED_SGMII_DUPLEX 26
785 +#define QCA955X_LED_SGMII_LINK_UP 27
786 +#define QCA955X_SGMII_SPEED0_INVERT 28
787 +#define QCA955X_SGMII_SPEED1_INVERT 29
788 +#define QCA955X_SGMII_DUPLEX_INVERT 30
789 +#define QCA955X_SGMII_LINK_UP_INVERT 31
790 +#define QCA955X_GE1_MII_MDO 32
791 +#define QCA955X_GE1_MII_MDC 33
792 +#define QCA955X_SWCOM2 38
793 +#define QCA955X_SWCOM3 39
794 +#define QCA955X_MAC2_GPIO 40
795 +#define QCA955X_MAC3_GPIO 41
796 +#define QCA955X_ATT_LED 42
797 +#define QCA955X_PWR_LED 43
798 +#define QCA955X_TX_FRAME 44
799 +#define QCA955X_RX_CLEAR_EXTERNAL 45
800 +#define QCA955X_LED_NETWORK_EN 46
801 +#define QCA955X_LED_POWER_EN 47
802 +#define QCA955X_WMAC_GLUE_WOW 68
803 +#define QCA955X_RX_CLEAR_EXTENSION 70
804 +#define QCA955X_CP_NAND_CS1 73
805 +#define QCA955X_USB_SUSPEND 74
806 +#define QCA955X_ETH_TX_ERR 75
807 +#define QCA955X_DDR_DQ_OE 76
808 +#define QCA955X_CLKREQ_N_EP 77
809 +#define QCA955X_CLKREQ_N_RC 78
810 +#define QCA955X_CLK_OBS0 79
811 +#define QCA955X_CLK_OBS1 80
812 +#define QCA955X_CLK_OBS2 81
813 +#define QCA955X_CLK_OBS3 82
814 +#define QCA955X_CLK_OBS4 83
815 +#define QCA955X_CLK_OBS5 84
820 +#define AR71XX_MII_REG_MII0_CTRL 0x00
821 +#define AR71XX_MII_REG_MII1_CTRL 0x04
823 +#define AR71XX_MII_CTRL_IF_MASK 3
824 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
825 +#define AR71XX_MII_CTRL_SPEED_MASK 3
826 +#define AR71XX_MII_CTRL_SPEED_10 0
827 +#define AR71XX_MII_CTRL_SPEED_100 1
828 +#define AR71XX_MII_CTRL_SPEED_1000 2
830 +#define AR71XX_MII0_CTRL_IF_GMII 0
831 +#define AR71XX_MII0_CTRL_IF_MII 1
832 +#define AR71XX_MII0_CTRL_IF_RGMII 2
833 +#define AR71XX_MII0_CTRL_IF_RMII 3
835 +#define AR71XX_MII1_CTRL_IF_RGMII 0
836 +#define AR71XX_MII1_CTRL_IF_RMII 1
839 + * AR933X GMAC interface
841 +#define AR933X_GMAC_REG_ETH_CFG 0x00
843 +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
844 +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
845 +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
846 +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
847 +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
848 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
849 +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
850 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
851 +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
852 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
853 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
856 + * AR934X GMAC Interface
858 +#define AR934X_GMAC_REG_ETH_CFG 0x00
860 +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
861 +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
862 +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
863 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
864 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
865 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
866 +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
867 +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
868 +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
869 +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
870 +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
871 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
872 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
873 +#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
874 +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
875 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
876 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
877 +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
878 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
881 + * QCA953X GMAC Interface
883 +#define QCA953X_GMAC_REG_ETH_CFG 0x00
885 +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
886 +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
887 +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
888 +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
891 + * QCA955X GMAC Interface
894 +#define QCA955X_GMAC_REG_ETH_CFG 0x00
895 +#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
897 +#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
898 +#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
899 +#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
900 +#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
901 +#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
902 +#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
903 +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
904 +#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
905 +#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
906 +#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
907 +#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
908 +#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
909 +#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
910 +#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
911 +#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
912 +#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
913 +#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
914 +#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
915 +#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
917 +#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
918 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
919 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
921 + * QCA956X GMAC Interface
924 +#define QCA956X_GMAC_REG_ETH_CFG 0x00
925 +#define QCA956X_GMAC_REG_SGMII_RESET 0x14
926 +#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
927 +#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
928 +#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
929 +#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
931 +#define QCA956X_ETH_CFG_RGMII_EN BIT(0)
932 +#define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
933 +#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
934 +#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
935 +#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
936 +#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
937 +#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
938 +#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
939 +#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14
940 +#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
941 +#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16
943 +#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
944 +#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
945 +#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
946 +#define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
947 +#define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
948 +#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
950 +#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
951 +#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1
952 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
953 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
954 +#define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
955 +#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
956 +#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
957 +#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
958 +#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
959 +#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
960 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
961 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
962 +#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27
963 +#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
965 +#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
966 +#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)
968 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
969 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
971 #endif /* __ASM_MACH_AR71XX_REGS_H */
projects / oweals / openwrt.git / blob