target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch

   1 From cb376159800b9b44be76949c3aee89eb06d29faa Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 6 Mar 2018 09:55:13 +0100
   4 Subject: [PATCH 07/27] irqchip/irq-ath79-intc: add irq cascade driver for
   5  QCA9556 SoCs
   6
   7 Signed-off-by: John Crispin <john@phrozen.org>
   8 ---
   9  drivers/irqchip/Makefile         |   1 +
  10  drivers/irqchip/irq-ath79-intc.c | 104 +++++++++++++++++++++++++++++++++++++++
  11  2 files changed, 105 insertions(+)
  12  create mode 100644 drivers/irqchip/irq-ath79-intc.c
  13
  14 --- a/drivers/irqchip/Makefile
  15 +++ b/drivers/irqchip/Makefile
  16 @@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP)                   += irqchip.o
  17
  18  obj-$(CONFIG_ALPINE_MSI)               += irq-alpine-msi.o
  19  obj-$(CONFIG_ATH79)                    += irq-ath79-cpu.o
  20 +obj-$(CONFIG_ATH79)                    += irq-ath79-intc.o
  21  obj-$(CONFIG_ATH79)                    += irq-ath79-misc.o
  22  obj-$(CONFIG_ARCH_BCM2835)             += irq-bcm2835.o
  23  obj-$(CONFIG_ARCH_BCM2835)             += irq-bcm2836.o
  24 --- /dev/null
  25 +++ b/drivers/irqchip/irq-ath79-intc.c
  26 @@ -0,0 +1,104 @@
  27 +/*
  28 + *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
  29 + *
  30 + *  Copyright (C) 2018 John Crispin <john@phrozen.org>
  31 + *
  32 + *  This program is free software; you can redistribute it and/or modify it
  33 + *  under the terms of the GNU General Public License version 2 as published
  34 + *  by the Free Software Foundation.
  35 + */
  36 +
  37 +#include <linux/interrupt.h>
  38 +#include <linux/irqchip.h>
  39 +#include <linux/of.h>
  40 +#include <linux/of_irq.h>
  41 +#include <linux/irqdomain.h>
  42 +
  43 +#include <asm/irq_cpu.h>
  44 +#include <asm/mach-ath79/ath79.h>
  45 +#include <asm/mach-ath79/ar71xx_regs.h>
  46 +
  47 +#define ATH79_MAX_INTC_CASCADE 3
  48 +
  49 +struct ath79_intc {
  50 +       struct irq_chip chip;
  51 +       u32 irq;
  52 +       u32 pending_mask;
  53 +       u32 irq_mask[ATH79_MAX_INTC_CASCADE];
  54 +};
  55 +
  56 +static void ath79_intc_irq_handler(struct irq_desc *desc)
  57 +{
  58 +       struct irq_domain *domain = irq_desc_get_handler_data(desc);
  59 +       struct ath79_intc *intc = domain->host_data;
  60 +       u32 pending;
  61 +
  62 +       pending = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
  63 +       pending &= intc->pending_mask;
  64 +
  65 +       if (pending) {
  66 +               int i;
  67 +
  68 +               for (i = 0; i < domain->hwirq_max; i++)
  69 +                       if (pending & intc->irq_mask[i])
  70 +                               generic_handle_irq(irq_find_mapping(domain, i));
  71 +       } else {
  72 +               spurious_interrupt();
  73 +       }
  74 +}
  75 +
  76 +static void ath79_intc_irq_unmask(struct irq_data *d)
  77 +{
  78 +}
  79 +
  80 +static void ath79_intc_irq_mask(struct irq_data *d)
  81 +{
  82 +}
  83 +
  84 +static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  85 +{
  86 +       struct ath79_intc *intc = d->host_data;
  87 +
  88 +       irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
  89 +
  90 +       return 0;
  91 +}
  92 +
  93 +static const struct irq_domain_ops ath79_irq_domain_ops = {
  94 +       .xlate = irq_domain_xlate_onecell,
  95 +       .map = ath79_intc_map,
  96 +};
  97 +
  98 +static int __init qca9556_intc_of_init(
  99 +       struct device_node *node, struct device_node *parent)
 100 +{
 101 +       struct irq_domain *domain;
 102 +       struct ath79_intc *intc;
 103 +       int cnt, i;
 104 +
 105 +       cnt = of_property_count_u32_elems(node, "qcom,pending-bits");
 106 +       if (cnt > ATH79_MAX_INTC_CASCADE)
 107 +               panic("Too many INTC pending bits\n");
 108 +
 109 +       intc = kzalloc(sizeof(*intc), GFP_KERNEL);
 110 +       if (!intc)
 111 +               panic("Failed to allocate INTC memory\n");
 112 +       intc->chip.name = "INTC";
 113 +       intc->chip.irq_unmask = ath79_intc_irq_unmask,
 114 +       intc->chip.irq_mask = ath79_intc_irq_mask,
 115 +
 116 +       of_property_read_u32_array(node, "qcom,pending-bits", intc->irq_mask, cnt);
 117 +       for (i = 0; i < cnt; i++)
 118 +               intc->pending_mask |= intc->irq_mask[i];
 119 +
 120 +       intc->irq = irq_of_parse_and_map(node, 0);
 121 +       if (!intc->irq)
 122 +               panic("Failed to get INTC IRQ");
 123 +
 124 +       domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
 125 +       irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
 126 +
 127 +       return 0;
 128 +}
 129 +IRQCHIP_DECLARE(qca9556_intc, "qcom,qca9556-intc",
 130 +               qca9556_intc_of_init);