target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/sizes.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_platform.h>
  18 #include "ag71xx.h"
  19
  20 #define AG71XX_DEFAULT_MSG_ENABLE       \
  21         (NETIF_MSG_DRV                  \
  22         | NETIF_MSG_PROBE               \
  23         | NETIF_MSG_LINK                \
  24         | NETIF_MSG_TIMER               \
  25         | NETIF_MSG_IFDOWN              \
  26         | NETIF_MSG_IFUP                \
  27         | NETIF_MSG_RX_ERR              \
  28         | NETIF_MSG_TX_ERR)
  29
  30 static int ag71xx_msg_level = -1;
  31
  32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  34
  35 #define ETH_SWITCH_HEADER_LEN   2
  36
  37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
  38
  39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
  40 {
  41         return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
  42 }
  43
  44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  45 {
  46         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  47                 ag->dev->name,
  48                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  49                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  50                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  51
  52         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  53                 ag->dev->name,
  54                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  55                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  56                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  57 }
  58
  59 static void ag71xx_dump_regs(struct ag71xx *ag)
  60 {
  61         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  62                 ag->dev->name,
  63                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  65                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  66                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  67                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  68         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  69                 ag->dev->name,
  70                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  71                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  72                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  73         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  74                 ag->dev->name,
  75                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  76                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  77                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  78         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  79                 ag->dev->name,
  80                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  81                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  82                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  83 }
  84
  85 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  86 {
  87         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  88                 ag->dev->name, label, intr,
  89                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  90                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  91                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  92                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  93                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  94                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  95 }
  96
  97 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
  98 {
  99         struct ag71xx_ring *ring = &ag->tx_ring;
 100         struct net_device *dev = ag->dev;
 101         int ring_mask = BIT(ring->order) - 1;
 102         u32 bytes_compl = 0, pkts_compl = 0;
 103
 104         while (ring->curr != ring->dirty) {
 105                 struct ag71xx_desc *desc;
 106                 u32 i = ring->dirty & ring_mask;
 107
 108                 desc = ag71xx_ring_desc(ring, i);
 109                 if (!ag71xx_desc_empty(desc)) {
 110                         desc->ctrl = 0;
 111                         dev->stats.tx_errors++;
 112                 }
 113
 114                 if (ring->buf[i].skb) {
 115                         bytes_compl += ring->buf[i].len;
 116                         pkts_compl++;
 117                         dev_kfree_skb_any(ring->buf[i].skb);
 118                 }
 119                 ring->buf[i].skb = NULL;
 120                 ring->dirty++;
 121         }
 122
 123         /* flush descriptors */
 124         wmb();
 125
 126         netdev_completed_queue(dev, pkts_compl, bytes_compl);
 127 }
 128
 129 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 130 {
 131         struct ag71xx_ring *ring = &ag->tx_ring;
 132         int ring_size = BIT(ring->order);
 133         int ring_mask = ring_size - 1;
 134         int i;
 135
 136         for (i = 0; i < ring_size; i++) {
 137                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
 138
 139                 desc->next = (u32) (ring->descs_dma +
 140                         AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
 141
 142                 desc->ctrl = DESC_EMPTY;
 143                 ring->buf[i].skb = NULL;
 144         }
 145
 146         /* flush descriptors */
 147         wmb();
 148
 149         ring->curr = 0;
 150         ring->dirty = 0;
 151         netdev_reset_queue(ag->dev);
 152 }
 153
 154 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 155 {
 156         struct ag71xx_ring *ring = &ag->rx_ring;
 157         int ring_size = BIT(ring->order);
 158         int i;
 159
 160         if (!ring->buf)
 161                 return;
 162
 163         for (i = 0; i < ring_size; i++)
 164                 if (ring->buf[i].rx_buf) {
 165                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
 166                                          ag->rx_buf_size, DMA_FROM_DEVICE);
 167                         skb_free_frag(ring->buf[i].rx_buf);
 168                 }
 169 }
 170
 171 static int ag71xx_buffer_size(struct ag71xx *ag)
 172 {
 173         return ag->rx_buf_size +
 174                SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 175 }
 176
 177 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
 178                                int offset,
 179                                void *(*alloc)(unsigned int size))
 180 {
 181         struct ag71xx_ring *ring = &ag->rx_ring;
 182         struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
 183         void *data;
 184
 185         data = alloc(ag71xx_buffer_size(ag));
 186         if (!data)
 187                 return false;
 188
 189         buf->rx_buf = data;
 190         buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
 191                                        DMA_FROM_DEVICE);
 192         desc->data = (u32) buf->dma_addr + offset;
 193         return true;
 194 }
 195
 196 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 197 {
 198         struct ag71xx_ring *ring = &ag->rx_ring;
 199         int ring_size = BIT(ring->order);
 200         int ring_mask = BIT(ring->order) - 1;
 201         unsigned int i;
 202         int ret;
 203
 204         ret = 0;
 205         for (i = 0; i < ring_size; i++) {
 206                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
 207
 208                 desc->next = (u32) (ring->descs_dma +
 209                         AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
 210
 211                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 212                         desc, desc->next);
 213         }
 214
 215         for (i = 0; i < ring_size; i++) {
 216                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
 217
 218                 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
 219                                         netdev_alloc_frag)) {
 220                         ret = -ENOMEM;
 221                         break;
 222                 }
 223
 224                 desc->ctrl = DESC_EMPTY;
 225         }
 226
 227         /* flush descriptors */
 228         wmb();
 229
 230         ring->curr = 0;
 231         ring->dirty = 0;
 232
 233         return ret;
 234 }
 235
 236 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 237 {
 238         struct ag71xx_ring *ring = &ag->rx_ring;
 239         int ring_mask = BIT(ring->order) - 1;
 240         unsigned int count;
 241         int offset = ag->rx_buf_offset;
 242
 243         count = 0;
 244         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 245                 struct ag71xx_desc *desc;
 246                 unsigned int i;
 247
 248                 i = ring->dirty & ring_mask;
 249                 desc = ag71xx_ring_desc(ring, i);
 250
 251                 if (!ring->buf[i].rx_buf &&
 252                     !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
 253                                         napi_alloc_frag))
 254                         break;
 255
 256                 desc->ctrl = DESC_EMPTY;
 257                 count++;
 258         }
 259
 260         /* flush descriptors */
 261         wmb();
 262
 263         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 264
 265         return count;
 266 }
 267
 268 static int ag71xx_rings_init(struct ag71xx *ag)
 269 {
 270         struct ag71xx_ring *tx = &ag->tx_ring;
 271         struct ag71xx_ring *rx = &ag->rx_ring;
 272         int ring_size = BIT(tx->order) + BIT(rx->order);
 273         int tx_size = BIT(tx->order);
 274
 275         tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
 276         if (!tx->buf)
 277                 return -ENOMEM;
 278
 279         tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
 280                                            &tx->descs_dma, GFP_ATOMIC);
 281         if (!tx->descs_cpu) {
 282                 kfree(tx->buf);
 283                 tx->buf = NULL;
 284                 return -ENOMEM;
 285         }
 286
 287         rx->buf = &tx->buf[BIT(tx->order)];
 288         rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
 289         rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
 290
 291         ag71xx_ring_tx_init(ag);
 292         return ag71xx_ring_rx_init(ag);
 293 }
 294
 295 static void ag71xx_rings_free(struct ag71xx *ag)
 296 {
 297         struct ag71xx_ring *tx = &ag->tx_ring;
 298         struct ag71xx_ring *rx = &ag->rx_ring;
 299         int ring_size = BIT(tx->order) + BIT(rx->order);
 300
 301         if (tx->descs_cpu)
 302                 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
 303                                   tx->descs_cpu, tx->descs_dma);
 304
 305         kfree(tx->buf);
 306
 307         tx->descs_cpu = NULL;
 308         rx->descs_cpu = NULL;
 309         tx->buf = NULL;
 310         rx->buf = NULL;
 311 }
 312
 313 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 314 {
 315         ag71xx_ring_rx_clean(ag);
 316         ag71xx_ring_tx_clean(ag);
 317         ag71xx_rings_free(ag);
 318
 319         netdev_reset_queue(ag->dev);
 320 }
 321
 322 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 323 {
 324         switch (ag->speed) {
 325         case SPEED_1000:
 326                 return "1000";
 327         case SPEED_100:
 328                 return "100";
 329         case SPEED_10:
 330                 return "10";
 331         }
 332
 333         return "?";
 334 }
 335
 336 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 337 {
 338         u32 t;
 339
 340         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
 341           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
 342
 343         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 344
 345         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
 346         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 347 }
 348
 349 static void ag71xx_dma_reset(struct ag71xx *ag)
 350 {
 351         u32 val;
 352         int i;
 353
 354         ag71xx_dump_dma_regs(ag);
 355
 356         /* stop RX and TX */
 357         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 358         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 359
 360         /*
 361          * give the hardware some time to really stop all rx/tx activity
 362          * clearing the descriptors too early causes random memory corruption
 363          */
 364         mdelay(1);
 365
 366         /* clear descriptor addresses */
 367         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
 368         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
 369
 370         /* clear pending RX/TX interrupts */
 371         for (i = 0; i < 256; i++) {
 372                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 373                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 374         }
 375
 376         /* clear pending errors */
 377         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 378         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 379
 380         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 381         if (val)
 382                 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
 383                          ag->dev->name, val);
 384
 385         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 386
 387         /* mask out reserved bits */
 388         val &= ~0xff000000;
 389
 390         if (val)
 391                 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
 392                          ag->dev->name, val);
 393
 394         ag71xx_dump_dma_regs(ag);
 395 }
 396
 397 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 398                          MAC_CFG1_SRX | MAC_CFG1_STX)
 399
 400 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 401
 402 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 403                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 404                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 405                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 406                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 407                          FIFO_CFG4_VT)
 408
 409 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 410                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 411                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 412                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 413                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 414                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 415
 416 static void ag71xx_hw_stop(struct ag71xx *ag)
 417 {
 418         /* disable all interrupts and stop the rx/tx engine */
 419         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 420         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 421         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 422 }
 423
 424 static void ag71xx_hw_setup(struct ag71xx *ag)
 425 {
 426         struct device_node *np = ag->pdev->dev.of_node;
 427         u32 init = MAC_CFG1_INIT;
 428
 429         /* setup MAC configuration registers */
 430         if (of_property_read_bool(np, "flow-control"))
 431                 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
 432         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
 433
 434         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 435                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 436
 437         /* setup max frame length to zero */
 438         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
 439
 440         /* setup FIFO configuration registers */
 441         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 442         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
 443         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
 444         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 445         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 446 }
 447
 448 static void ag71xx_hw_init(struct ag71xx *ag)
 449 {
 450         ag71xx_hw_stop(ag);
 451
 452         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 453         udelay(20);
 454
 455         reset_control_assert(ag->mac_reset);
 456         msleep(100);
 457         reset_control_deassert(ag->mac_reset);
 458         msleep(200);
 459
 460         ag71xx_hw_setup(ag);
 461
 462         ag71xx_dma_reset(ag);
 463 }
 464
 465 static void ag71xx_fast_reset(struct ag71xx *ag)
 466 {
 467         struct net_device *dev = ag->dev;
 468         u32 rx_ds;
 469         u32 mii_reg;
 470
 471         ag71xx_hw_stop(ag);
 472         wmb();
 473
 474         mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
 475         rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
 476
 477         ag71xx_tx_packets(ag, true);
 478
 479         reset_control_assert(ag->mac_reset);
 480         udelay(10);
 481         reset_control_deassert(ag->mac_reset);
 482         udelay(10);
 483
 484         ag71xx_dma_reset(ag);
 485         ag71xx_hw_setup(ag);
 486         ag->tx_ring.curr = 0;
 487         ag->tx_ring.dirty = 0;
 488         netdev_reset_queue(ag->dev);
 489
 490         /* setup max frame length */
 491         ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
 492                   ag71xx_max_frame_len(ag->dev->mtu));
 493
 494         ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
 495         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 496         ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
 497
 498         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 499 }
 500
 501 static void ag71xx_hw_start(struct ag71xx *ag)
 502 {
 503         /* start RX engine */
 504         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 505
 506         /* enable interrupts */
 507         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 508
 509         netif_wake_queue(ag->dev);
 510 }
 511
 512 static void ath79_set_pllval(struct ag71xx *ag)
 513 {
 514         u32 pll_reg = ag->pllreg[1];
 515         u32 pll_val;
 516
 517         if (!ag->pllregmap)
 518                 return;
 519
 520         switch (ag->speed) {
 521         case SPEED_10:
 522                 pll_val = ag->plldata[2];
 523                 break;
 524         case SPEED_100:
 525                 pll_val = ag->plldata[1];
 526                 break;
 527         case SPEED_1000:
 528                 pll_val = ag->plldata[0];
 529                 break;
 530         default:
 531                 BUG();
 532         }
 533
 534         if (pll_val)
 535                 regmap_write(ag->pllregmap, pll_reg, pll_val);
 536 }
 537
 538 static void ath79_set_pll(struct ag71xx *ag)
 539 {
 540         u32 pll_cfg = ag->pllreg[0];
 541         u32 pll_shift = ag->pllreg[2];
 542
 543         if (!ag->pllregmap)
 544                 return;
 545
 546         regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
 547         udelay(100);
 548
 549         ath79_set_pllval(ag);
 550
 551         regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
 552         udelay(100);
 553
 554         regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
 555         udelay(100);
 556 }
 557
 558 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
 559 {
 560         u32 t;
 561
 562         t = __raw_readl(ag->mii_base);
 563         t &= ~(AR71XX_MII_CTRL_IF_MASK);
 564         t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
 565         __raw_writel(t, ag->mii_base);
 566 }
 567
 568 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
 569 {
 570         unsigned int mii_if;
 571
 572         switch (ag->phy_if_mode) {
 573         case PHY_INTERFACE_MODE_MII:
 574                 mii_if = AR71XX_MII0_CTRL_IF_MII;
 575                 break;
 576         case PHY_INTERFACE_MODE_GMII:
 577                 mii_if = AR71XX_MII0_CTRL_IF_GMII;
 578                 break;
 579         case PHY_INTERFACE_MODE_RGMII:
 580                 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
 581                 break;
 582         case PHY_INTERFACE_MODE_RMII:
 583                 mii_if = AR71XX_MII0_CTRL_IF_RMII;
 584                 break;
 585         default:
 586                 WARN(1, "Impossible PHY mode defined.\n");
 587                 return;
 588         }
 589
 590         ath79_mii_ctrl_set_if(ag, mii_if);
 591 }
 592
 593 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
 594 {
 595         unsigned int mii_if;
 596
 597         switch (ag->phy_if_mode) {
 598         case PHY_INTERFACE_MODE_RMII:
 599                 mii_if = AR71XX_MII1_CTRL_IF_RMII;
 600                 break;
 601         case PHY_INTERFACE_MODE_RGMII:
 602                 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
 603                 break;
 604         default:
 605                 WARN(1, "Impossible PHY mode defined.\n");
 606                 return;
 607         }
 608
 609         ath79_mii_ctrl_set_if(ag, mii_if);
 610 }
 611
 612 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
 613 {
 614         unsigned int mii_speed;
 615         u32 t;
 616
 617         if (!ag->mii_base)
 618                 return;
 619
 620         switch (ag->speed) {
 621         case SPEED_10:
 622                 mii_speed =  AR71XX_MII_CTRL_SPEED_10;
 623                 break;
 624         case SPEED_100:
 625                 mii_speed =  AR71XX_MII_CTRL_SPEED_100;
 626                 break;
 627         case SPEED_1000:
 628                 mii_speed =  AR71XX_MII_CTRL_SPEED_1000;
 629                 break;
 630         default:
 631                 BUG();
 632         }
 633
 634         t = __raw_readl(ag->mii_base);
 635         t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
 636         t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
 637         __raw_writel(t, ag->mii_base);
 638 }
 639
 640 static void
 641 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
 642 {
 643         struct device_node *np = ag->pdev->dev.of_node;
 644         u32 cfg2;
 645         u32 ifctl;
 646         u32 fifo5;
 647
 648         if (!ag->link && update) {
 649                 ag71xx_hw_stop(ag);
 650                 netif_carrier_off(ag->dev);
 651                 if (netif_msg_link(ag))
 652                         pr_info("%s: link down\n", ag->dev->name);
 653                 return;
 654         }
 655
 656         if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
 657             !of_device_is_compatible(np, "qca,ar7100-eth"))
 658                 ag71xx_fast_reset(ag);
 659
 660         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
 661         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
 662         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
 663
 664         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
 665         ifctl &= ~(MAC_IFCTL_SPEED);
 666
 667         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 668         fifo5 &= ~FIFO_CFG5_BM;
 669
 670         switch (ag->speed) {
 671         case SPEED_1000:
 672                 cfg2 |= MAC_CFG2_IF_1000;
 673                 fifo5 |= FIFO_CFG5_BM;
 674                 break;
 675         case SPEED_100:
 676                 cfg2 |= MAC_CFG2_IF_10_100;
 677                 ifctl |= MAC_IFCTL_SPEED;
 678                 break;
 679         case SPEED_10:
 680                 cfg2 |= MAC_CFG2_IF_10_100;
 681                 break;
 682         default:
 683                 BUG();
 684                 return;
 685         }
 686
 687         if (ag->tx_ring.desc_split) {
 688                 ag->fifodata[2] &= 0xffff;
 689                 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
 690         }
 691
 692         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
 693
 694         if (update) {
 695                 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
 696                     of_device_is_compatible(np, "qca,ar9130-eth")) {
 697                         ath79_set_pll(ag);
 698                         ath79_mii_ctrl_set_speed(ag);
 699                 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
 700                            of_device_is_compatible(np, "qca,ar9340-eth") ||
 701                            of_device_is_compatible(np, "qca,qca9550-eth") ||
 702                            of_device_is_compatible(np, "qca,qca9560-eth")) {
 703                         ath79_set_pllval(ag);
 704                 }
 705         }
 706
 707         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 708         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 709         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 710
 711         if (of_device_is_compatible(np, "qca,qca9530-eth") ||
 712             of_device_is_compatible(np, "qca,qca9560-eth")) {
 713                 /*
 714                  * The rx ring buffer can stall on small packets on QCA953x and
 715                  * QCA956x. Disabling the inline checksum engine fixes the stall.
 716                  * The wr, rr functions cannot be used since this hidden register
 717                  * is outside of the normal ag71xx register block.
 718                  */
 719                 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
 720                 if (dam) {
 721                         __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
 722                         (void)__raw_readl(dam);
 723                         iounmap(dam);
 724                 }
 725         }
 726
 727         ag71xx_hw_start(ag);
 728
 729         netif_carrier_on(ag->dev);
 730         if (update && netif_msg_link(ag))
 731                 pr_info("%s: link up (%sMbps/%s duplex)\n",
 732                         ag->dev->name,
 733                         ag71xx_speed_str(ag),
 734                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 735
 736         ag71xx_dump_regs(ag);
 737 }
 738
 739 void ag71xx_link_adjust(struct ag71xx *ag)
 740 {
 741         __ag71xx_link_adjust(ag, true);
 742 }
 743
 744 static int ag71xx_hw_enable(struct ag71xx *ag)
 745 {
 746         int ret;
 747
 748         ret = ag71xx_rings_init(ag);
 749         if (ret)
 750                 return ret;
 751
 752         napi_enable(&ag->napi);
 753         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 754         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 755         netif_start_queue(ag->dev);
 756
 757         return 0;
 758 }
 759
 760 static void ag71xx_hw_disable(struct ag71xx *ag)
 761 {
 762         unsigned long flags;
 763
 764         spin_lock_irqsave(&ag->lock, flags);
 765
 766         netif_stop_queue(ag->dev);
 767
 768         ag71xx_hw_stop(ag);
 769         ag71xx_dma_reset(ag);
 770
 771         napi_disable(&ag->napi);
 772         del_timer_sync(&ag->oom_timer);
 773
 774         spin_unlock_irqrestore(&ag->lock, flags);
 775
 776         ag71xx_rings_cleanup(ag);
 777 }
 778
 779 static int ag71xx_open(struct net_device *dev)
 780 {
 781         struct ag71xx *ag = netdev_priv(dev);
 782         unsigned int max_frame_len;
 783         int ret;
 784
 785         netif_carrier_off(dev);
 786         max_frame_len = ag71xx_max_frame_len(dev->mtu);
 787         ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
 788
 789         /* setup max frame length */
 790         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
 791         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 792
 793         ret = ag71xx_hw_enable(ag);
 794         if (ret)
 795                 goto err;
 796
 797         phy_start(ag->phy_dev);
 798
 799         return 0;
 800
 801 err:
 802         ag71xx_rings_cleanup(ag);
 803         return ret;
 804 }
 805
 806 static int ag71xx_stop(struct net_device *dev)
 807 {
 808         unsigned long flags;
 809         struct ag71xx *ag = netdev_priv(dev);
 810
 811         netif_carrier_off(dev);
 812         phy_stop(ag->phy_dev);
 813
 814         spin_lock_irqsave(&ag->lock, flags);
 815         if (ag->link) {
 816                 ag->link = 0;
 817                 ag71xx_link_adjust(ag);
 818         }
 819         spin_unlock_irqrestore(&ag->lock, flags);
 820
 821         ag71xx_hw_disable(ag);
 822
 823         return 0;
 824 }
 825
 826 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
 827 {
 828         int i;
 829         struct ag71xx_desc *desc;
 830         int ring_mask = BIT(ring->order) - 1;
 831         int ndesc = 0;
 832         int split = ring->desc_split;
 833
 834         if (!split)
 835                 split = len;
 836
 837         while (len > 0) {
 838                 unsigned int cur_len = len;
 839
 840                 i = (ring->curr + ndesc) & ring_mask;
 841                 desc = ag71xx_ring_desc(ring, i);
 842
 843                 if (!ag71xx_desc_empty(desc))
 844                         return -1;
 845
 846                 if (cur_len > split) {
 847                         cur_len = split;
 848
 849                         /*
 850                          * TX will hang if DMA transfers <= 4 bytes,
 851                          * make sure next segment is more than 4 bytes long.
 852                          */
 853                         if (len <= split + 4)
 854                                 cur_len -= 4;
 855                 }
 856
 857                 desc->data = addr;
 858                 addr += cur_len;
 859                 len -= cur_len;
 860
 861                 if (len > 0)
 862                         cur_len |= DESC_MORE;
 863
 864                 /* prevent early tx attempt of this descriptor */
 865                 if (!ndesc)
 866                         cur_len |= DESC_EMPTY;
 867
 868                 desc->ctrl = cur_len;
 869                 ndesc++;
 870         }
 871
 872         return ndesc;
 873 }
 874
 875 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 876                                           struct net_device *dev)
 877 {
 878         struct ag71xx *ag = netdev_priv(dev);
 879         struct ag71xx_ring *ring = &ag->tx_ring;
 880         int ring_mask = BIT(ring->order) - 1;
 881         int ring_size = BIT(ring->order);
 882         struct ag71xx_desc *desc;
 883         dma_addr_t dma_addr;
 884         int i, n, ring_min;
 885
 886         if (skb->len <= 4) {
 887                 DBG("%s: packet len is too small\n", ag->dev->name);
 888                 goto err_drop;
 889         }
 890
 891         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 892                                   DMA_TO_DEVICE);
 893
 894         i = ring->curr & ring_mask;
 895         desc = ag71xx_ring_desc(ring, i);
 896
 897         /* setup descriptor fields */
 898         n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
 899         if (n < 0)
 900                 goto err_drop_unmap;
 901
 902         i = (ring->curr + n - 1) & ring_mask;
 903         ring->buf[i].len = skb->len;
 904         ring->buf[i].skb = skb;
 905
 906         netdev_sent_queue(dev, skb->len);
 907
 908         skb_tx_timestamp(skb);
 909
 910         desc->ctrl &= ~DESC_EMPTY;
 911         ring->curr += n;
 912
 913         /* flush descriptor */
 914         wmb();
 915
 916         ring_min = 2;
 917         if (ring->desc_split)
 918             ring_min *= AG71XX_TX_RING_DS_PER_PKT;
 919
 920         if (ring->curr - ring->dirty >= ring_size - ring_min) {
 921                 DBG("%s: tx queue full\n", dev->name);
 922                 netif_stop_queue(dev);
 923         }
 924
 925         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 926
 927         /* enable TX engine */
 928         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 929
 930         return NETDEV_TX_OK;
 931
 932 err_drop_unmap:
 933         dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
 934
 935 err_drop:
 936         dev->stats.tx_dropped++;
 937
 938         dev_kfree_skb(skb);
 939         return NETDEV_TX_OK;
 940 }
 941
 942 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 943 {
 944         struct ag71xx *ag = netdev_priv(dev);
 945         int ret;
 946
 947         switch (cmd) {
 948         case SIOCETHTOOL:
 949                 if (ag->phy_dev == NULL)
 950                         break;
 951
 952                 spin_lock_irq(&ag->lock);
 953                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 954                 spin_unlock_irq(&ag->lock);
 955                 return ret;
 956
 957         case SIOCSIFHWADDR:
 958                 if (copy_from_user
 959                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 960                         return -EFAULT;
 961                 return 0;
 962
 963         case SIOCGIFHWADDR:
 964                 if (copy_to_user
 965                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 966                         return -EFAULT;
 967                 return 0;
 968
 969         case SIOCGMIIPHY:
 970         case SIOCGMIIREG:
 971         case SIOCSMIIREG:
 972                 if (ag->phy_dev == NULL)
 973                         break;
 974
 975                 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
 976
 977         default:
 978                 break;
 979         }
 980
 981         return -EOPNOTSUPP;
 982 }
 983
 984 static void ag71xx_oom_timer_handler(unsigned long data)
 985 {
 986         struct net_device *dev = (struct net_device *) data;
 987         struct ag71xx *ag = netdev_priv(dev);
 988
 989         napi_schedule(&ag->napi);
 990 }
 991
 992 static void ag71xx_tx_timeout(struct net_device *dev)
 993 {
 994         struct ag71xx *ag = netdev_priv(dev);
 995
 996         if (netif_msg_tx_err(ag))
 997                 pr_info("%s: tx timeout\n", ag->dev->name);
 998
 999         schedule_delayed_work(&ag->restart_work, 1);
1000 }
1001
1002 static void ag71xx_restart_work_func(struct work_struct *work)
1003 {
1004         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
1005
1006         rtnl_lock();
1007         ag71xx_hw_disable(ag);
1008         ag71xx_hw_enable(ag);
1009         if (ag->link)
1010                 __ag71xx_link_adjust(ag, false);
1011         rtnl_unlock();
1012 }
1013
1014 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
1015 {
1016         unsigned long timestamp;
1017         u32 rx_sm, tx_sm, rx_fd;
1018
1019         timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1020         if (likely(time_before(jiffies, timestamp + HZ/10)))
1021                 return false;
1022
1023         if (!netif_carrier_ok(ag->dev))
1024                 return false;
1025
1026         rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1027         if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1028                 return true;
1029
1030         tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1031         rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1032         if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1033             ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1034                 return true;
1035
1036         return false;
1037 }
1038
1039 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1040 {
1041         struct ag71xx_ring *ring = &ag->tx_ring;
1042         bool dma_stuck = false;
1043         int ring_mask = BIT(ring->order) - 1;
1044         int ring_size = BIT(ring->order);
1045         int sent = 0;
1046         int bytes_compl = 0;
1047         int n = 0;
1048
1049         DBG("%s: processing TX ring\n", ag->dev->name);
1050
1051         while (ring->dirty + n != ring->curr) {
1052                 unsigned int i = (ring->dirty + n) & ring_mask;
1053                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1054                 struct sk_buff *skb = ring->buf[i].skb;
1055
1056                 if (!flush && !ag71xx_desc_empty(desc)) {
1057                         if (ag->tx_hang_workaround &&
1058                             ag71xx_check_dma_stuck(ag)) {
1059                                 schedule_delayed_work(&ag->restart_work, HZ / 2);
1060                                 dma_stuck = true;
1061                         }
1062                         break;
1063                 }
1064
1065                 if (flush)
1066                         desc->ctrl |= DESC_EMPTY;
1067
1068                 n++;
1069                 if (!skb)
1070                         continue;
1071
1072                 dev_kfree_skb_any(skb);
1073                 ring->buf[i].skb = NULL;
1074
1075                 bytes_compl += ring->buf[i].len;
1076
1077                 sent++;
1078                 ring->dirty += n;
1079
1080                 while (n > 0) {
1081                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1082                         n--;
1083                 }
1084         }
1085
1086         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1087
1088         if (!sent)
1089                 return 0;
1090
1091         ag->dev->stats.tx_bytes += bytes_compl;
1092         ag->dev->stats.tx_packets += sent;
1093
1094         netdev_completed_queue(ag->dev, sent, bytes_compl);
1095         if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1096                 netif_wake_queue(ag->dev);
1097
1098         if (!dma_stuck)
1099                 cancel_delayed_work(&ag->restart_work);
1100
1101         return sent;
1102 }
1103
1104 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1105 {
1106         struct net_device *dev = ag->dev;
1107         struct ag71xx_ring *ring = &ag->rx_ring;
1108         unsigned int pktlen_mask = ag->desc_pktlen_mask;
1109         unsigned int offset = ag->rx_buf_offset;
1110         int ring_mask = BIT(ring->order) - 1;
1111         int ring_size = BIT(ring->order);
1112         struct sk_buff_head queue;
1113         struct sk_buff *skb;
1114         int done = 0;
1115
1116         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1117                         dev->name, limit, ring->curr, ring->dirty);
1118
1119         skb_queue_head_init(&queue);
1120
1121         while (done < limit) {
1122                 unsigned int i = ring->curr & ring_mask;
1123                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1124                 int pktlen;
1125                 int err = 0;
1126
1127                 if (ag71xx_desc_empty(desc))
1128                         break;
1129
1130                 if ((ring->dirty + ring_size) == ring->curr) {
1131                         ag71xx_assert(0);
1132                         break;
1133                 }
1134
1135                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1136
1137                 pktlen = desc->ctrl & pktlen_mask;
1138                 pktlen -= ETH_FCS_LEN;
1139
1140                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1141                                  ag->rx_buf_size, DMA_FROM_DEVICE);
1142
1143                 dev->stats.rx_packets++;
1144                 dev->stats.rx_bytes += pktlen;
1145
1146                 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1147                 if (!skb) {
1148                         skb_free_frag(ring->buf[i].rx_buf);
1149                         goto next;
1150                 }
1151
1152                 skb_reserve(skb, offset);
1153                 skb_put(skb, pktlen);
1154
1155                 if (err) {
1156                         dev->stats.rx_dropped++;
1157                         kfree_skb(skb);
1158                 } else {
1159                         skb->dev = dev;
1160                         skb->ip_summed = CHECKSUM_NONE;
1161                         __skb_queue_tail(&queue, skb);
1162                 }
1163
1164 next:
1165                 ring->buf[i].rx_buf = NULL;
1166                 done++;
1167
1168                 ring->curr++;
1169         }
1170
1171         ag71xx_ring_rx_refill(ag);
1172
1173         while ((skb = __skb_dequeue(&queue)) != NULL) {
1174                 skb->protocol = eth_type_trans(skb, dev);
1175                 netif_receive_skb(skb);
1176         }
1177
1178         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1179                 dev->name, ring->curr, ring->dirty, done);
1180
1181         return done;
1182 }
1183
1184 static int ag71xx_poll(struct napi_struct *napi, int limit)
1185 {
1186         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1187         struct net_device *dev = ag->dev;
1188         struct ag71xx_ring *rx_ring = &ag->rx_ring;
1189         int rx_ring_size = BIT(rx_ring->order);
1190         unsigned long flags;
1191         u32 status;
1192         int tx_done;
1193         int rx_done;
1194
1195         tx_done = ag71xx_tx_packets(ag, false);
1196
1197         DBG("%s: processing RX ring\n", dev->name);
1198         rx_done = ag71xx_rx_packets(ag, limit);
1199
1200         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1201
1202         if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1203                 goto oom;
1204
1205         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1206         if (unlikely(status & RX_STATUS_OF)) {
1207                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1208                 dev->stats.rx_fifo_errors++;
1209
1210                 /* restart RX */
1211                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1212         }
1213
1214         if (rx_done < limit) {
1215                 if (status & RX_STATUS_PR)
1216                         goto more;
1217
1218                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1219                 if (status & TX_STATUS_PS)
1220                         goto more;
1221
1222                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1223                         dev->name, rx_done, tx_done, limit);
1224
1225                 napi_complete(napi);
1226
1227                 /* enable interrupts */
1228                 spin_lock_irqsave(&ag->lock, flags);
1229                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1230                 spin_unlock_irqrestore(&ag->lock, flags);
1231                 return rx_done;
1232         }
1233
1234 more:
1235         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1236                         dev->name, rx_done, tx_done, limit);
1237         return limit;
1238
1239 oom:
1240         if (netif_msg_rx_err(ag))
1241                 pr_info("%s: out of memory\n", dev->name);
1242
1243         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1244         napi_complete(napi);
1245         return 0;
1246 }
1247
1248 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1249 {
1250         struct net_device *dev = dev_id;
1251         struct ag71xx *ag = netdev_priv(dev);
1252         u32 status;
1253
1254         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1255         ag71xx_dump_intr(ag, "raw", status);
1256
1257         if (unlikely(!status))
1258                 return IRQ_NONE;
1259
1260         if (unlikely(status & AG71XX_INT_ERR)) {
1261                 if (status & AG71XX_INT_TX_BE) {
1262                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1263                         dev_err(&dev->dev, "TX BUS error\n");
1264                 }
1265                 if (status & AG71XX_INT_RX_BE) {
1266                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1267                         dev_err(&dev->dev, "RX BUS error\n");
1268                 }
1269         }
1270
1271         if (likely(status & AG71XX_INT_POLL)) {
1272                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1273                 DBG("%s: enable polling mode\n", dev->name);
1274                 napi_schedule(&ag->napi);
1275         }
1276
1277         ag71xx_debugfs_update_int_stats(ag, status);
1278
1279         return IRQ_HANDLED;
1280 }
1281
1282 #ifdef CONFIG_NET_POLL_CONTROLLER
1283 /*
1284  * Polling 'interrupt' - used by things like netconsole to send skbs
1285  * without having to re-enable interrupts. It's not called while
1286  * the interrupt routine is executing.
1287  */
1288 static void ag71xx_netpoll(struct net_device *dev)
1289 {
1290         disable_irq(dev->irq);
1291         ag71xx_interrupt(dev->irq, dev);
1292         enable_irq(dev->irq);
1293 }
1294 #endif
1295
1296 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1297 {
1298         struct ag71xx *ag = netdev_priv(dev);
1299
1300         dev->mtu = new_mtu;
1301         ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1302                   ag71xx_max_frame_len(dev->mtu));
1303
1304         return 0;
1305 }
1306
1307 static const struct net_device_ops ag71xx_netdev_ops = {
1308         .ndo_open               = ag71xx_open,
1309         .ndo_stop               = ag71xx_stop,
1310         .ndo_start_xmit         = ag71xx_hard_start_xmit,
1311         .ndo_do_ioctl           = ag71xx_do_ioctl,
1312         .ndo_tx_timeout         = ag71xx_tx_timeout,
1313         .ndo_change_mtu         = ag71xx_change_mtu,
1314         .ndo_set_mac_address    = eth_mac_addr,
1315         .ndo_validate_addr      = eth_validate_addr,
1316 #ifdef CONFIG_NET_POLL_CONTROLLER
1317         .ndo_poll_controller    = ag71xx_netpoll,
1318 #endif
1319 };
1320
1321 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1322 {
1323         switch (mode) {
1324         case PHY_INTERFACE_MODE_MII:
1325                 return "MII";
1326         case PHY_INTERFACE_MODE_GMII:
1327                 return "GMII";
1328         case PHY_INTERFACE_MODE_RMII:
1329                 return "RMII";
1330         case PHY_INTERFACE_MODE_RGMII:
1331                 return "RGMII";
1332         case PHY_INTERFACE_MODE_SGMII:
1333                 return "SGMII";
1334         default:
1335                 break;
1336         }
1337
1338         return "unknown";
1339 }
1340
1341 static int ag71xx_probe(struct platform_device *pdev)
1342 {
1343         struct device_node *np = pdev->dev.of_node;
1344         struct device_node *mdio_node;
1345         struct net_device *dev;
1346         struct resource *res;
1347         struct ag71xx *ag;
1348         const void *mac_addr;
1349         u32 max_frame_len;
1350         int tx_size, err;
1351
1352         if (!np)
1353                 return -ENODEV;
1354
1355         dev = alloc_etherdev(sizeof(*ag));
1356         if (!dev)
1357                 return -ENOMEM;
1358
1359         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1360         if (!res)
1361                 return -EINVAL;
1362
1363         err = ag71xx_setup_gmac(np);
1364         if (err)
1365                 return err;
1366
1367         SET_NETDEV_DEV(dev, &pdev->dev);
1368
1369         ag = netdev_priv(dev);
1370         ag->pdev = pdev;
1371         ag->dev = dev;
1372         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1373                                         AG71XX_DEFAULT_MSG_ENABLE);
1374         spin_lock_init(&ag->lock);
1375
1376         ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac");
1377         if (IS_ERR(ag->mac_reset)) {
1378                 dev_err(&pdev->dev, "missing mac reset\n");
1379                 err = PTR_ERR(ag->mac_reset);
1380                 goto err_free;
1381         }
1382
1383         if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1384                 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1385                     of_device_is_compatible(np, "qca,ar7100-eth")) {
1386                         ag->fifodata[0] = 0x0fff0000;
1387                         ag->fifodata[1] = 0x00001fff;
1388                 } else {
1389                         ag->fifodata[0] = 0x0010ffff;
1390                         ag->fifodata[1] = 0x015500aa;
1391                         ag->fifodata[2] = 0x01f00140;
1392                 }
1393                 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1394                         ag->fifodata[2] = 0x00780fff;
1395                 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1396                         ag->fifodata[2] = 0x008001ff;
1397         }
1398
1399         if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1400                 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1401
1402         if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1403                 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1404
1405         ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1406         if (IS_ERR(ag->pllregmap)) {
1407                 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1408                 ag->pllregmap = NULL;
1409         }
1410
1411         ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1412                                             res->end - res->start + 1);
1413         if (!ag->mac_base) {
1414                 err = -ENOMEM;
1415                 goto err_free;
1416         }
1417         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1418         if (res) {
1419                 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1420                                             res->end - res->start + 1);
1421                 if (!ag->mii_base) {
1422                         err = -ENOMEM;
1423                         goto err_free;
1424                 }
1425         }
1426
1427         dev->irq = platform_get_irq(pdev, 0);
1428         err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1429                                0x0, dev_name(&pdev->dev), dev);
1430         if (err) {
1431                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1432                 goto err_free;
1433         }
1434
1435         dev->netdev_ops = &ag71xx_netdev_ops;
1436         dev->ethtool_ops = &ag71xx_ethtool_ops;
1437
1438         INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1439
1440         init_timer(&ag->oom_timer);
1441         ag->oom_timer.data = (unsigned long) dev;
1442         ag->oom_timer.function = ag71xx_oom_timer_handler;
1443
1444         tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1445         ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1446
1447         if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1448             of_device_is_compatible(np, "qca,qca9530-eth") ||
1449             of_device_is_compatible(np, "qca,qca9550-eth") ||
1450             of_device_is_compatible(np, "qca,qca9560-eth"))
1451                 ag->desc_pktlen_mask = SZ_16K - 1;
1452         else
1453                 ag->desc_pktlen_mask = SZ_4K - 1;
1454
1455         if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1456             !of_device_is_compatible(np, "qca,qca9550-eth") &&
1457             !of_device_is_compatible(np, "qca,qca9560-eth"))
1458                 max_frame_len = ag->desc_pktlen_mask;
1459         else
1460                 max_frame_len = 1540;
1461
1462         dev->min_mtu = 68;
1463         dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1464
1465         if (of_device_is_compatible(np, "qca,ar7240-eth"))
1466                 ag->tx_hang_workaround = 1;
1467
1468         ag->rx_buf_offset = NET_SKB_PAD;
1469         if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1470             !of_device_is_compatible(np, "qca,ar9130-eth"))
1471                 ag->rx_buf_offset += NET_IP_ALIGN;
1472
1473         if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1474                 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1475                 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1476         }
1477         ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1478
1479         ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1480                                             sizeof(struct ag71xx_desc),
1481                                             &ag->stop_desc_dma, GFP_KERNEL);
1482         if (!ag->stop_desc)
1483                 goto err_free;
1484
1485         ag->stop_desc->data = 0;
1486         ag->stop_desc->ctrl = 0;
1487         ag->stop_desc->next = (u32) ag->stop_desc_dma;
1488
1489         mac_addr = of_get_mac_address(np);
1490         if (mac_addr)
1491                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1492         if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1493                 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1494                 eth_random_addr(dev->dev_addr);
1495         }
1496
1497         ag->phy_if_mode = of_get_phy_mode(np);
1498         if (ag->phy_if_mode < 0) {
1499                 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1500                 err = ag->phy_if_mode;
1501                 goto err_free;
1502         }
1503
1504         if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1505                 ag->mac_idx = -1;
1506         if (ag->mii_base)
1507                 switch (ag->mac_idx) {
1508                 case 0:
1509                         ath79_mii0_ctrl_set_if(ag);
1510                         break;
1511                 case 1:
1512                         ath79_mii1_ctrl_set_if(ag);
1513                         break;
1514                 default:
1515                         break;
1516                 }
1517
1518         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1519
1520         ag71xx_dump_regs(ag);
1521
1522         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1523
1524         ag71xx_hw_init(ag);
1525
1526         ag71xx_dump_regs(ag);
1527
1528         if (!of_device_is_compatible(np, "simple-mfd")) {
1529                 mdio_node = of_get_child_by_name(np, "mdio-bus");
1530                 if (!IS_ERR(mdio_node))
1531                         of_platform_device_create(mdio_node, NULL, NULL);
1532         }
1533
1534         err = ag71xx_phy_connect(ag);
1535         if (err)
1536                 goto err_free;
1537
1538         err = ag71xx_debugfs_init(ag);
1539         if (err)
1540                 goto err_phy_disconnect;
1541
1542         platform_set_drvdata(pdev, dev);
1543
1544         err = register_netdev(dev);
1545         if (err) {
1546                 dev_err(&pdev->dev, "unable to register net device\n");
1547                 platform_set_drvdata(pdev, NULL);
1548                 ag71xx_debugfs_exit(ag);
1549                 goto err_phy_disconnect;
1550         }
1551
1552         pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1553                 dev->name, (unsigned long) ag->mac_base, dev->irq,
1554                 ag71xx_get_phy_if_mode_name(ag->phy_if_mode));
1555
1556         return 0;
1557
1558 err_phy_disconnect:
1559         ag71xx_phy_disconnect(ag);
1560 err_free:
1561         free_netdev(dev);
1562         return err;
1563 }
1564
1565 static int ag71xx_remove(struct platform_device *pdev)
1566 {
1567         struct net_device *dev = platform_get_drvdata(pdev);
1568         struct ag71xx *ag;
1569
1570         if (!dev)
1571                 return 0;
1572
1573         ag = netdev_priv(dev);
1574         ag71xx_debugfs_exit(ag);
1575         ag71xx_phy_disconnect(ag);
1576         unregister_netdev(dev);
1577         free_irq(dev->irq, dev);
1578         iounmap(ag->mac_base);
1579         kfree(dev);
1580         platform_set_drvdata(pdev, NULL);
1581
1582         return 0;
1583 }
1584
1585 static const struct of_device_id ag71xx_match[] = {
1586         { .compatible = "qca,ar7100-eth" },
1587         { .compatible = "qca,ar7240-eth" },
1588         { .compatible = "qca,ar7241-eth" },
1589         { .compatible = "qca,ar7242-eth" },
1590         { .compatible = "qca,ar9130-eth" },
1591         { .compatible = "qca,ar9330-eth" },
1592         { .compatible = "qca,ar9340-eth" },
1593         { .compatible = "qca,qca9530-eth" },
1594         { .compatible = "qca,qca9550-eth" },
1595         { .compatible = "qca,qca9560-eth" },
1596         {}
1597 };
1598
1599 static struct platform_driver ag71xx_driver = {
1600         .probe          = ag71xx_probe,
1601         .remove         = ag71xx_remove,
1602         .driver = {
1603                 .name   = AG71XX_DRV_NAME,
1604                 .of_match_table = ag71xx_match,
1605         }
1606 };
1607
1608 static int __init ag71xx_module_init(void)
1609 {
1610         int ret;
1611
1612         ret = ag71xx_debugfs_root_init();
1613         if (ret)
1614                 goto err_out;
1615
1616         ret = platform_driver_register(&ag71xx_driver);
1617         if (ret)
1618                 goto err_debugfs_exit;
1619
1620         return 0;
1621
1622 err_debugfs_exit:
1623         ag71xx_debugfs_root_exit();
1624 err_out:
1625         return ret;
1626 }
1627
1628 static void __exit ag71xx_module_exit(void)
1629 {
1630         platform_driver_unregister(&ag71xx_driver);
1631         ag71xx_debugfs_root_exit();
1632 }
1633
1634 module_init(ag71xx_module_init);
1635 module_exit(ag71xx_module_exit);
1636
1637 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1638 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1639 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1640 MODULE_LICENSE("GPL v2");
1641 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);