target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/sizes.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_platform.h>
  18 #include "ag71xx.h"
  19
  20 #define AG71XX_DEFAULT_MSG_ENABLE       \
  21         (NETIF_MSG_DRV                  \
  22         | NETIF_MSG_PROBE               \
  23         | NETIF_MSG_LINK                \
  24         | NETIF_MSG_TIMER               \
  25         | NETIF_MSG_IFDOWN              \
  26         | NETIF_MSG_IFUP                \
  27         | NETIF_MSG_RX_ERR              \
  28         | NETIF_MSG_TX_ERR)
  29
  30 static int ag71xx_msg_level = -1;
  31
  32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  34
  35 #define ETH_SWITCH_HEADER_LEN   2
  36
  37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
  38
  39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
  40 {
  41         return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
  42 }
  43
  44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  45 {
  46         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  47                 ag->dev->name,
  48                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  49                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  50                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  51
  52         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  53                 ag->dev->name,
  54                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  55                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  56                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  57 }
  58
  59 static void ag71xx_dump_regs(struct ag71xx *ag)
  60 {
  61         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  62                 ag->dev->name,
  63                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  65                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  66                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  67                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  68         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  69                 ag->dev->name,
  70                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  71                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  72                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  73         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  74                 ag->dev->name,
  75                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  76                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  77                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  78         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  79                 ag->dev->name,
  80                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  81                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  82                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  83 }
  84
  85 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  86 {
  87         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  88                 ag->dev->name, label, intr,
  89                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  90                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  91                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  92                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  93                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  94                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  95 }
  96
  97 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
  98 {
  99         struct ag71xx_ring *ring = &ag->tx_ring;
 100         struct net_device *dev = ag->dev;
 101         int ring_mask = BIT(ring->order) - 1;
 102         u32 bytes_compl = 0, pkts_compl = 0;
 103
 104         while (ring->curr != ring->dirty) {
 105                 struct ag71xx_desc *desc;
 106                 u32 i = ring->dirty & ring_mask;
 107
 108                 desc = ag71xx_ring_desc(ring, i);
 109                 if (!ag71xx_desc_empty(desc)) {
 110                         desc->ctrl = 0;
 111                         dev->stats.tx_errors++;
 112                 }
 113
 114                 if (ring->buf[i].skb) {
 115                         bytes_compl += ring->buf[i].len;
 116                         pkts_compl++;
 117                         dev_kfree_skb_any(ring->buf[i].skb);
 118                 }
 119                 ring->buf[i].skb = NULL;
 120                 ring->dirty++;
 121         }
 122
 123         /* flush descriptors */
 124         wmb();
 125
 126         netdev_completed_queue(dev, pkts_compl, bytes_compl);
 127 }
 128
 129 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 130 {
 131         struct ag71xx_ring *ring = &ag->tx_ring;
 132         int ring_size = BIT(ring->order);
 133         int ring_mask = ring_size - 1;
 134         int i;
 135
 136         for (i = 0; i < ring_size; i++) {
 137                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
 138
 139                 desc->next = (u32) (ring->descs_dma +
 140                         AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
 141
 142                 desc->ctrl = DESC_EMPTY;
 143                 ring->buf[i].skb = NULL;
 144         }
 145
 146         /* flush descriptors */
 147         wmb();
 148
 149         ring->curr = 0;
 150         ring->dirty = 0;
 151         netdev_reset_queue(ag->dev);
 152 }
 153
 154 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 155 {
 156         struct ag71xx_ring *ring = &ag->rx_ring;
 157         int ring_size = BIT(ring->order);
 158         int i;
 159
 160         if (!ring->buf)
 161                 return;
 162
 163         for (i = 0; i < ring_size; i++)
 164                 if (ring->buf[i].rx_buf) {
 165                         dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
 166                                          ag->rx_buf_size, DMA_FROM_DEVICE);
 167                         skb_free_frag(ring->buf[i].rx_buf);
 168                 }
 169 }
 170
 171 static int ag71xx_buffer_size(struct ag71xx *ag)
 172 {
 173         return ag->rx_buf_size +
 174                SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 175 }
 176
 177 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
 178                                int offset,
 179                                void *(*alloc)(unsigned int size))
 180 {
 181         struct ag71xx_ring *ring = &ag->rx_ring;
 182         struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
 183         void *data;
 184
 185         data = alloc(ag71xx_buffer_size(ag));
 186         if (!data)
 187                 return false;
 188
 189         buf->rx_buf = data;
 190         buf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
 191                                        DMA_FROM_DEVICE);
 192         desc->data = (u32) buf->dma_addr + offset;
 193         return true;
 194 }
 195
 196 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 197 {
 198         struct ag71xx_ring *ring = &ag->rx_ring;
 199         int ring_size = BIT(ring->order);
 200         int ring_mask = BIT(ring->order) - 1;
 201         unsigned int i;
 202         int ret;
 203
 204         ret = 0;
 205         for (i = 0; i < ring_size; i++) {
 206                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
 207
 208                 desc->next = (u32) (ring->descs_dma +
 209                         AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
 210
 211                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 212                         desc, desc->next);
 213         }
 214
 215         for (i = 0; i < ring_size; i++) {
 216                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
 217
 218                 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
 219                                         netdev_alloc_frag)) {
 220                         ret = -ENOMEM;
 221                         break;
 222                 }
 223
 224                 desc->ctrl = DESC_EMPTY;
 225         }
 226
 227         /* flush descriptors */
 228         wmb();
 229
 230         ring->curr = 0;
 231         ring->dirty = 0;
 232
 233         return ret;
 234 }
 235
 236 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 237 {
 238         struct ag71xx_ring *ring = &ag->rx_ring;
 239         int ring_mask = BIT(ring->order) - 1;
 240         unsigned int count;
 241         int offset = ag->rx_buf_offset;
 242
 243         count = 0;
 244         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 245                 struct ag71xx_desc *desc;
 246                 unsigned int i;
 247
 248                 i = ring->dirty & ring_mask;
 249                 desc = ag71xx_ring_desc(ring, i);
 250
 251                 if (!ring->buf[i].rx_buf &&
 252                     !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
 253                                         napi_alloc_frag))
 254                         break;
 255
 256                 desc->ctrl = DESC_EMPTY;
 257                 count++;
 258         }
 259
 260         /* flush descriptors */
 261         wmb();
 262
 263         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 264
 265         return count;
 266 }
 267
 268 static int ag71xx_rings_init(struct ag71xx *ag)
 269 {
 270         struct ag71xx_ring *tx = &ag->tx_ring;
 271         struct ag71xx_ring *rx = &ag->rx_ring;
 272         int ring_size = BIT(tx->order) + BIT(rx->order);
 273         int tx_size = BIT(tx->order);
 274
 275         tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
 276         if (!tx->buf)
 277                 return -ENOMEM;
 278
 279         tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
 280                                            &tx->descs_dma, GFP_ATOMIC);
 281         if (!tx->descs_cpu) {
 282                 kfree(tx->buf);
 283                 tx->buf = NULL;
 284                 return -ENOMEM;
 285         }
 286
 287         rx->buf = &tx->buf[BIT(tx->order)];
 288         rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
 289         rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
 290
 291         ag71xx_ring_tx_init(ag);
 292         return ag71xx_ring_rx_init(ag);
 293 }
 294
 295 static void ag71xx_rings_free(struct ag71xx *ag)
 296 {
 297         struct ag71xx_ring *tx = &ag->tx_ring;
 298         struct ag71xx_ring *rx = &ag->rx_ring;
 299         int ring_size = BIT(tx->order) + BIT(rx->order);
 300
 301         if (tx->descs_cpu)
 302                 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
 303                                   tx->descs_cpu, tx->descs_dma);
 304
 305         kfree(tx->buf);
 306
 307         tx->descs_cpu = NULL;
 308         rx->descs_cpu = NULL;
 309         tx->buf = NULL;
 310         rx->buf = NULL;
 311 }
 312
 313 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 314 {
 315         ag71xx_ring_rx_clean(ag);
 316         ag71xx_ring_tx_clean(ag);
 317         ag71xx_rings_free(ag);
 318
 319         netdev_reset_queue(ag->dev);
 320 }
 321
 322 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 323 {
 324         switch (ag->speed) {
 325         case SPEED_1000:
 326                 return "1000";
 327         case SPEED_100:
 328                 return "100";
 329         case SPEED_10:
 330                 return "10";
 331         }
 332
 333         return "?";
 334 }
 335
 336 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 337 {
 338         u32 t;
 339
 340         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
 341           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
 342
 343         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 344
 345         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
 346         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 347 }
 348
 349 static void ag71xx_dma_reset(struct ag71xx *ag)
 350 {
 351         u32 val;
 352         int i;
 353
 354         ag71xx_dump_dma_regs(ag);
 355
 356         /* stop RX and TX */
 357         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 358         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 359
 360         /*
 361          * give the hardware some time to really stop all rx/tx activity
 362          * clearing the descriptors too early causes random memory corruption
 363          */
 364         mdelay(1);
 365
 366         /* clear descriptor addresses */
 367         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
 368         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
 369
 370         /* clear pending RX/TX interrupts */
 371         for (i = 0; i < 256; i++) {
 372                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 373                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 374         }
 375
 376         /* clear pending errors */
 377         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 378         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 379
 380         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 381         if (val)
 382                 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
 383                          ag->dev->name, val);
 384
 385         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 386
 387         /* mask out reserved bits */
 388         val &= ~0xff000000;
 389
 390         if (val)
 391                 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
 392                          ag->dev->name, val);
 393
 394         ag71xx_dump_dma_regs(ag);
 395 }
 396
 397 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 398                          MAC_CFG1_SRX | MAC_CFG1_STX)
 399
 400 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 401
 402 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 403                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 404                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 405                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 406                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 407                          FIFO_CFG4_VT)
 408
 409 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 410                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 411                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 412                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 413                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 414                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 415
 416 static void ag71xx_hw_stop(struct ag71xx *ag)
 417 {
 418         /* disable all interrupts and stop the rx/tx engine */
 419         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 420         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 421         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 422 }
 423
 424 static void ag71xx_hw_setup(struct ag71xx *ag)
 425 {
 426         struct device_node *np = ag->pdev->dev.of_node;
 427         u32 init = MAC_CFG1_INIT;
 428
 429         /* setup MAC configuration registers */
 430         if (of_property_read_bool(np, "flow-control"))
 431                 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
 432         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
 433
 434         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 435                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 436
 437         /* setup max frame length to zero */
 438         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
 439
 440         /* setup FIFO configuration registers */
 441         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 442         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
 443         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
 444         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 445         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 446 }
 447
 448 static void ag71xx_hw_init(struct ag71xx *ag)
 449 {
 450         ag71xx_hw_stop(ag);
 451
 452         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 453         udelay(20);
 454
 455         reset_control_assert(ag->mac_reset);
 456         if (ag->mdio_reset)
 457                 reset_control_assert(ag->mdio_reset);
 458         msleep(100);
 459         reset_control_deassert(ag->mac_reset);
 460         if (ag->mdio_reset)
 461                 reset_control_deassert(ag->mdio_reset);
 462         msleep(200);
 463
 464         ag71xx_hw_setup(ag);
 465
 466         ag71xx_dma_reset(ag);
 467 }
 468
 469 static void ag71xx_fast_reset(struct ag71xx *ag)
 470 {
 471         struct net_device *dev = ag->dev;
 472         u32 rx_ds;
 473         u32 mii_reg;
 474
 475         ag71xx_hw_stop(ag);
 476         wmb();
 477
 478         mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
 479         rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
 480
 481         ag71xx_tx_packets(ag, true);
 482
 483         reset_control_assert(ag->mac_reset);
 484         udelay(10);
 485         reset_control_deassert(ag->mac_reset);
 486         udelay(10);
 487
 488         ag71xx_dma_reset(ag);
 489         ag71xx_hw_setup(ag);
 490         ag->tx_ring.curr = 0;
 491         ag->tx_ring.dirty = 0;
 492         netdev_reset_queue(ag->dev);
 493
 494         /* setup max frame length */
 495         ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
 496                   ag71xx_max_frame_len(ag->dev->mtu));
 497
 498         ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
 499         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 500         ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
 501
 502         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 503 }
 504
 505 static void ag71xx_hw_start(struct ag71xx *ag)
 506 {
 507         /* start RX engine */
 508         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 509
 510         /* enable interrupts */
 511         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 512
 513         netif_wake_queue(ag->dev);
 514 }
 515
 516 static void ath79_set_pllval(struct ag71xx *ag)
 517 {
 518         u32 pll_reg = ag->pllreg[1];
 519         u32 pll_val;
 520
 521         if (!ag->pllregmap)
 522                 return;
 523
 524         switch (ag->speed) {
 525         case SPEED_10:
 526                 pll_val = ag->plldata[2];
 527                 break;
 528         case SPEED_100:
 529                 pll_val = ag->plldata[1];
 530                 break;
 531         case SPEED_1000:
 532                 pll_val = ag->plldata[0];
 533                 break;
 534         default:
 535                 BUG();
 536         }
 537
 538         if (pll_val)
 539                 regmap_write(ag->pllregmap, pll_reg, pll_val);
 540 }
 541
 542 static void ath79_set_pll(struct ag71xx *ag)
 543 {
 544         u32 pll_cfg = ag->pllreg[0];
 545         u32 pll_shift = ag->pllreg[2];
 546
 547         if (!ag->pllregmap)
 548                 return;
 549
 550         regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
 551         udelay(100);
 552
 553         ath79_set_pllval(ag);
 554
 555         regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
 556         udelay(100);
 557
 558         regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
 559         udelay(100);
 560 }
 561
 562 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
 563 {
 564         u32 t;
 565
 566         t = __raw_readl(ag->mii_base);
 567         t &= ~(AR71XX_MII_CTRL_IF_MASK);
 568         t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
 569         __raw_writel(t, ag->mii_base);
 570 }
 571
 572 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
 573 {
 574         unsigned int mii_if;
 575
 576         switch (ag->phy_if_mode) {
 577         case PHY_INTERFACE_MODE_MII:
 578                 mii_if = AR71XX_MII0_CTRL_IF_MII;
 579                 break;
 580         case PHY_INTERFACE_MODE_GMII:
 581                 mii_if = AR71XX_MII0_CTRL_IF_GMII;
 582                 break;
 583         case PHY_INTERFACE_MODE_RGMII:
 584                 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
 585                 break;
 586         case PHY_INTERFACE_MODE_RMII:
 587                 mii_if = AR71XX_MII0_CTRL_IF_RMII;
 588                 break;
 589         default:
 590                 WARN(1, "Impossible PHY mode defined.\n");
 591                 return;
 592         }
 593
 594         ath79_mii_ctrl_set_if(ag, mii_if);
 595 }
 596
 597 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
 598 {
 599         unsigned int mii_if;
 600
 601         switch (ag->phy_if_mode) {
 602         case PHY_INTERFACE_MODE_RMII:
 603                 mii_if = AR71XX_MII1_CTRL_IF_RMII;
 604                 break;
 605         case PHY_INTERFACE_MODE_RGMII:
 606                 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
 607                 break;
 608         default:
 609                 WARN(1, "Impossible PHY mode defined.\n");
 610                 return;
 611         }
 612
 613         ath79_mii_ctrl_set_if(ag, mii_if);
 614 }
 615
 616 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
 617 {
 618         unsigned int mii_speed;
 619         u32 t;
 620
 621         if (!ag->mii_base)
 622                 return;
 623
 624         switch (ag->speed) {
 625         case SPEED_10:
 626                 mii_speed =  AR71XX_MII_CTRL_SPEED_10;
 627                 break;
 628         case SPEED_100:
 629                 mii_speed =  AR71XX_MII_CTRL_SPEED_100;
 630                 break;
 631         case SPEED_1000:
 632                 mii_speed =  AR71XX_MII_CTRL_SPEED_1000;
 633                 break;
 634         default:
 635                 BUG();
 636         }
 637
 638         t = __raw_readl(ag->mii_base);
 639         t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
 640         t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
 641         __raw_writel(t, ag->mii_base);
 642 }
 643
 644 static void
 645 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
 646 {
 647         struct device_node *np = ag->pdev->dev.of_node;
 648         u32 cfg2;
 649         u32 ifctl;
 650         u32 fifo5;
 651
 652         if (!ag->link && update) {
 653                 ag71xx_hw_stop(ag);
 654                 netif_carrier_off(ag->dev);
 655                 if (netif_msg_link(ag))
 656                         pr_info("%s: link down\n", ag->dev->name);
 657                 return;
 658         }
 659
 660         if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
 661             !of_device_is_compatible(np, "qca,ar7100-eth"))
 662                 ag71xx_fast_reset(ag);
 663
 664         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
 665         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
 666         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
 667
 668         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
 669         ifctl &= ~(MAC_IFCTL_SPEED);
 670
 671         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 672         fifo5 &= ~FIFO_CFG5_BM;
 673
 674         switch (ag->speed) {
 675         case SPEED_1000:
 676                 cfg2 |= MAC_CFG2_IF_1000;
 677                 fifo5 |= FIFO_CFG5_BM;
 678                 break;
 679         case SPEED_100:
 680                 cfg2 |= MAC_CFG2_IF_10_100;
 681                 ifctl |= MAC_IFCTL_SPEED;
 682                 break;
 683         case SPEED_10:
 684                 cfg2 |= MAC_CFG2_IF_10_100;
 685                 break;
 686         default:
 687                 BUG();
 688                 return;
 689         }
 690
 691         if (ag->tx_ring.desc_split) {
 692                 ag->fifodata[2] &= 0xffff;
 693                 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
 694         }
 695
 696         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
 697
 698         if (update) {
 699                 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
 700                     of_device_is_compatible(np, "qca,ar9130-eth")) {
 701                         ath79_set_pll(ag);
 702                         ath79_mii_ctrl_set_speed(ag);
 703                 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
 704                            of_device_is_compatible(np, "qca,ar9340-eth") ||
 705                            of_device_is_compatible(np, "qca,qca9550-eth") ||
 706                            of_device_is_compatible(np, "qca,qca9560-eth")) {
 707                         ath79_set_pllval(ag);
 708                 }
 709         }
 710
 711         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 712         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 713         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 714
 715         if (of_device_is_compatible(np, "qca,qca9530-eth") ||
 716             of_device_is_compatible(np, "qca,qca9560-eth")) {
 717                 /*
 718                  * The rx ring buffer can stall on small packets on QCA953x and
 719                  * QCA956x. Disabling the inline checksum engine fixes the stall.
 720                  * The wr, rr functions cannot be used since this hidden register
 721                  * is outside of the normal ag71xx register block.
 722                  */
 723                 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
 724                 if (dam) {
 725                         __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
 726                         (void)__raw_readl(dam);
 727                         iounmap(dam);
 728                 }
 729         }
 730
 731         ag71xx_hw_start(ag);
 732
 733         netif_carrier_on(ag->dev);
 734         if (update && netif_msg_link(ag))
 735                 pr_info("%s: link up (%sMbps/%s duplex)\n",
 736                         ag->dev->name,
 737                         ag71xx_speed_str(ag),
 738                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 739
 740         ag71xx_dump_regs(ag);
 741 }
 742
 743 void ag71xx_link_adjust(struct ag71xx *ag)
 744 {
 745         __ag71xx_link_adjust(ag, true);
 746 }
 747
 748 static int ag71xx_hw_enable(struct ag71xx *ag)
 749 {
 750         int ret;
 751
 752         ret = ag71xx_rings_init(ag);
 753         if (ret)
 754                 return ret;
 755
 756         napi_enable(&ag->napi);
 757         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 758         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 759         netif_start_queue(ag->dev);
 760
 761         return 0;
 762 }
 763
 764 static void ag71xx_hw_disable(struct ag71xx *ag)
 765 {
 766         unsigned long flags;
 767
 768         spin_lock_irqsave(&ag->lock, flags);
 769
 770         netif_stop_queue(ag->dev);
 771
 772         ag71xx_hw_stop(ag);
 773         ag71xx_dma_reset(ag);
 774
 775         napi_disable(&ag->napi);
 776         del_timer_sync(&ag->oom_timer);
 777
 778         spin_unlock_irqrestore(&ag->lock, flags);
 779
 780         ag71xx_rings_cleanup(ag);
 781 }
 782
 783 static int ag71xx_open(struct net_device *dev)
 784 {
 785         struct ag71xx *ag = netdev_priv(dev);
 786         unsigned int max_frame_len;
 787         int ret;
 788
 789         netif_carrier_off(dev);
 790         max_frame_len = ag71xx_max_frame_len(dev->mtu);
 791         ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
 792
 793         /* setup max frame length */
 794         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
 795         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 796
 797         ret = ag71xx_hw_enable(ag);
 798         if (ret)
 799                 goto err;
 800
 801         phy_start(ag->phy_dev);
 802
 803         return 0;
 804
 805 err:
 806         ag71xx_rings_cleanup(ag);
 807         return ret;
 808 }
 809
 810 static int ag71xx_stop(struct net_device *dev)
 811 {
 812         unsigned long flags;
 813         struct ag71xx *ag = netdev_priv(dev);
 814
 815         netif_carrier_off(dev);
 816         phy_stop(ag->phy_dev);
 817
 818         spin_lock_irqsave(&ag->lock, flags);
 819         if (ag->link) {
 820                 ag->link = 0;
 821                 ag71xx_link_adjust(ag);
 822         }
 823         spin_unlock_irqrestore(&ag->lock, flags);
 824
 825         ag71xx_hw_disable(ag);
 826
 827         return 0;
 828 }
 829
 830 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
 831 {
 832         int i;
 833         struct ag71xx_desc *desc;
 834         int ring_mask = BIT(ring->order) - 1;
 835         int ndesc = 0;
 836         int split = ring->desc_split;
 837
 838         if (!split)
 839                 split = len;
 840
 841         while (len > 0) {
 842                 unsigned int cur_len = len;
 843
 844                 i = (ring->curr + ndesc) & ring_mask;
 845                 desc = ag71xx_ring_desc(ring, i);
 846
 847                 if (!ag71xx_desc_empty(desc))
 848                         return -1;
 849
 850                 if (cur_len > split) {
 851                         cur_len = split;
 852
 853                         /*
 854                          * TX will hang if DMA transfers <= 4 bytes,
 855                          * make sure next segment is more than 4 bytes long.
 856                          */
 857                         if (len <= split + 4)
 858                                 cur_len -= 4;
 859                 }
 860
 861                 desc->data = addr;
 862                 addr += cur_len;
 863                 len -= cur_len;
 864
 865                 if (len > 0)
 866                         cur_len |= DESC_MORE;
 867
 868                 /* prevent early tx attempt of this descriptor */
 869                 if (!ndesc)
 870                         cur_len |= DESC_EMPTY;
 871
 872                 desc->ctrl = cur_len;
 873                 ndesc++;
 874         }
 875
 876         return ndesc;
 877 }
 878
 879 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 880                                           struct net_device *dev)
 881 {
 882         struct ag71xx *ag = netdev_priv(dev);
 883         struct ag71xx_ring *ring = &ag->tx_ring;
 884         int ring_mask = BIT(ring->order) - 1;
 885         int ring_size = BIT(ring->order);
 886         struct ag71xx_desc *desc;
 887         dma_addr_t dma_addr;
 888         int i, n, ring_min;
 889
 890         if (skb->len <= 4) {
 891                 DBG("%s: packet len is too small\n", ag->dev->name);
 892                 goto err_drop;
 893         }
 894
 895         dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
 896                                   DMA_TO_DEVICE);
 897
 898         i = ring->curr & ring_mask;
 899         desc = ag71xx_ring_desc(ring, i);
 900
 901         /* setup descriptor fields */
 902         n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
 903         if (n < 0)
 904                 goto err_drop_unmap;
 905
 906         i = (ring->curr + n - 1) & ring_mask;
 907         ring->buf[i].len = skb->len;
 908         ring->buf[i].skb = skb;
 909
 910         netdev_sent_queue(dev, skb->len);
 911
 912         skb_tx_timestamp(skb);
 913
 914         desc->ctrl &= ~DESC_EMPTY;
 915         ring->curr += n;
 916
 917         /* flush descriptor */
 918         wmb();
 919
 920         ring_min = 2;
 921         if (ring->desc_split)
 922             ring_min *= AG71XX_TX_RING_DS_PER_PKT;
 923
 924         if (ring->curr - ring->dirty >= ring_size - ring_min) {
 925                 DBG("%s: tx queue full\n", dev->name);
 926                 netif_stop_queue(dev);
 927         }
 928
 929         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 930
 931         /* enable TX engine */
 932         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 933
 934         return NETDEV_TX_OK;
 935
 936 err_drop_unmap:
 937         dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
 938
 939 err_drop:
 940         dev->stats.tx_dropped++;
 941
 942         dev_kfree_skb(skb);
 943         return NETDEV_TX_OK;
 944 }
 945
 946 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 947 {
 948         struct ag71xx *ag = netdev_priv(dev);
 949         int ret;
 950
 951         switch (cmd) {
 952         case SIOCETHTOOL:
 953                 if (ag->phy_dev == NULL)
 954                         break;
 955
 956                 spin_lock_irq(&ag->lock);
 957                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 958                 spin_unlock_irq(&ag->lock);
 959                 return ret;
 960
 961         case SIOCSIFHWADDR:
 962                 if (copy_from_user
 963                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 964                         return -EFAULT;
 965                 return 0;
 966
 967         case SIOCGIFHWADDR:
 968                 if (copy_to_user
 969                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 970                         return -EFAULT;
 971                 return 0;
 972
 973         case SIOCGMIIPHY:
 974         case SIOCGMIIREG:
 975         case SIOCSMIIREG:
 976                 if (ag->phy_dev == NULL)
 977                         break;
 978
 979                 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
 980
 981         default:
 982                 break;
 983         }
 984
 985         return -EOPNOTSUPP;
 986 }
 987
 988 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
 989 static void ag71xx_oom_timer_handler(unsigned long data)
 990 {
 991         struct net_device *dev = (struct net_device *) data;
 992         struct ag71xx *ag = netdev_priv(dev);
 993 #else
 994 static void ag71xx_oom_timer_handler(struct timer_list *t)
 995 {
 996         struct ag71xx *ag = from_timer(ag, t, oom_timer);
 997 #endif
 998
 999         napi_schedule(&ag->napi);
1000 }
1001
1002 static void ag71xx_tx_timeout(struct net_device *dev)
1003 {
1004         struct ag71xx *ag = netdev_priv(dev);
1005
1006         if (netif_msg_tx_err(ag))
1007                 pr_info("%s: tx timeout\n", ag->dev->name);
1008
1009         schedule_delayed_work(&ag->restart_work, 1);
1010 }
1011
1012 static void ag71xx_restart_work_func(struct work_struct *work)
1013 {
1014         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
1015
1016         rtnl_lock();
1017         ag71xx_hw_disable(ag);
1018         ag71xx_hw_enable(ag);
1019         if (ag->link)
1020                 __ag71xx_link_adjust(ag, false);
1021         rtnl_unlock();
1022 }
1023
1024 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
1025 {
1026         unsigned long timestamp;
1027         u32 rx_sm, tx_sm, rx_fd;
1028
1029         timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1030         if (likely(time_before(jiffies, timestamp + HZ/10)))
1031                 return false;
1032
1033         if (!netif_carrier_ok(ag->dev))
1034                 return false;
1035
1036         rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1037         if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1038                 return true;
1039
1040         tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1041         rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1042         if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1043             ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1044                 return true;
1045
1046         return false;
1047 }
1048
1049 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1050 {
1051         struct ag71xx_ring *ring = &ag->tx_ring;
1052         bool dma_stuck = false;
1053         int ring_mask = BIT(ring->order) - 1;
1054         int ring_size = BIT(ring->order);
1055         int sent = 0;
1056         int bytes_compl = 0;
1057         int n = 0;
1058
1059         DBG("%s: processing TX ring\n", ag->dev->name);
1060
1061         while (ring->dirty + n != ring->curr) {
1062                 unsigned int i = (ring->dirty + n) & ring_mask;
1063                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1064                 struct sk_buff *skb = ring->buf[i].skb;
1065
1066                 if (!flush && !ag71xx_desc_empty(desc)) {
1067                         if (ag->tx_hang_workaround &&
1068                             ag71xx_check_dma_stuck(ag)) {
1069                                 schedule_delayed_work(&ag->restart_work, HZ / 2);
1070                                 dma_stuck = true;
1071                         }
1072                         break;
1073                 }
1074
1075                 if (flush)
1076                         desc->ctrl |= DESC_EMPTY;
1077
1078                 n++;
1079                 if (!skb)
1080                         continue;
1081
1082                 dev_kfree_skb_any(skb);
1083                 ring->buf[i].skb = NULL;
1084
1085                 bytes_compl += ring->buf[i].len;
1086
1087                 sent++;
1088                 ring->dirty += n;
1089
1090                 while (n > 0) {
1091                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1092                         n--;
1093                 }
1094         }
1095
1096         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1097
1098         if (!sent)
1099                 return 0;
1100
1101         ag->dev->stats.tx_bytes += bytes_compl;
1102         ag->dev->stats.tx_packets += sent;
1103
1104         netdev_completed_queue(ag->dev, sent, bytes_compl);
1105         if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1106                 netif_wake_queue(ag->dev);
1107
1108         if (!dma_stuck)
1109                 cancel_delayed_work(&ag->restart_work);
1110
1111         return sent;
1112 }
1113
1114 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1115 {
1116         struct net_device *dev = ag->dev;
1117         struct ag71xx_ring *ring = &ag->rx_ring;
1118         unsigned int pktlen_mask = ag->desc_pktlen_mask;
1119         unsigned int offset = ag->rx_buf_offset;
1120         int ring_mask = BIT(ring->order) - 1;
1121         int ring_size = BIT(ring->order);
1122         struct sk_buff_head queue;
1123         struct sk_buff *skb;
1124         int done = 0;
1125
1126         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1127                         dev->name, limit, ring->curr, ring->dirty);
1128
1129         skb_queue_head_init(&queue);
1130
1131         while (done < limit) {
1132                 unsigned int i = ring->curr & ring_mask;
1133                 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1134                 int pktlen;
1135                 int err = 0;
1136
1137                 if (ag71xx_desc_empty(desc))
1138                         break;
1139
1140                 if ((ring->dirty + ring_size) == ring->curr) {
1141                         ag71xx_assert(0);
1142                         break;
1143                 }
1144
1145                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1146
1147                 pktlen = desc->ctrl & pktlen_mask;
1148                 pktlen -= ETH_FCS_LEN;
1149
1150                 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
1151                                  ag->rx_buf_size, DMA_FROM_DEVICE);
1152
1153                 dev->stats.rx_packets++;
1154                 dev->stats.rx_bytes += pktlen;
1155
1156                 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1157                 if (!skb) {
1158                         skb_free_frag(ring->buf[i].rx_buf);
1159                         goto next;
1160                 }
1161
1162                 skb_reserve(skb, offset);
1163                 skb_put(skb, pktlen);
1164
1165                 if (err) {
1166                         dev->stats.rx_dropped++;
1167                         kfree_skb(skb);
1168                 } else {
1169                         skb->dev = dev;
1170                         skb->ip_summed = CHECKSUM_NONE;
1171                         __skb_queue_tail(&queue, skb);
1172                 }
1173
1174 next:
1175                 ring->buf[i].rx_buf = NULL;
1176                 done++;
1177
1178                 ring->curr++;
1179         }
1180
1181         ag71xx_ring_rx_refill(ag);
1182
1183         while ((skb = __skb_dequeue(&queue)) != NULL) {
1184                 skb->protocol = eth_type_trans(skb, dev);
1185                 netif_receive_skb(skb);
1186         }
1187
1188         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1189                 dev->name, ring->curr, ring->dirty, done);
1190
1191         return done;
1192 }
1193
1194 static int ag71xx_poll(struct napi_struct *napi, int limit)
1195 {
1196         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1197         struct net_device *dev = ag->dev;
1198         struct ag71xx_ring *rx_ring = &ag->rx_ring;
1199         int rx_ring_size = BIT(rx_ring->order);
1200         unsigned long flags;
1201         u32 status;
1202         int tx_done;
1203         int rx_done;
1204
1205         tx_done = ag71xx_tx_packets(ag, false);
1206
1207         DBG("%s: processing RX ring\n", dev->name);
1208         rx_done = ag71xx_rx_packets(ag, limit);
1209
1210         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1211
1212         if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1213                 goto oom;
1214
1215         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1216         if (unlikely(status & RX_STATUS_OF)) {
1217                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1218                 dev->stats.rx_fifo_errors++;
1219
1220                 /* restart RX */
1221                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1222         }
1223
1224         if (rx_done < limit) {
1225                 if (status & RX_STATUS_PR)
1226                         goto more;
1227
1228                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1229                 if (status & TX_STATUS_PS)
1230                         goto more;
1231
1232                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1233                         dev->name, rx_done, tx_done, limit);
1234
1235                 napi_complete(napi);
1236
1237                 /* enable interrupts */
1238                 spin_lock_irqsave(&ag->lock, flags);
1239                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1240                 spin_unlock_irqrestore(&ag->lock, flags);
1241                 return rx_done;
1242         }
1243
1244 more:
1245         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1246                         dev->name, rx_done, tx_done, limit);
1247         return limit;
1248
1249 oom:
1250         if (netif_msg_rx_err(ag))
1251                 pr_info("%s: out of memory\n", dev->name);
1252
1253         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1254         napi_complete(napi);
1255         return 0;
1256 }
1257
1258 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1259 {
1260         struct net_device *dev = dev_id;
1261         struct ag71xx *ag = netdev_priv(dev);
1262         u32 status;
1263
1264         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1265         ag71xx_dump_intr(ag, "raw", status);
1266
1267         if (unlikely(!status))
1268                 return IRQ_NONE;
1269
1270         if (unlikely(status & AG71XX_INT_ERR)) {
1271                 if (status & AG71XX_INT_TX_BE) {
1272                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1273                         dev_err(&dev->dev, "TX BUS error\n");
1274                 }
1275                 if (status & AG71XX_INT_RX_BE) {
1276                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1277                         dev_err(&dev->dev, "RX BUS error\n");
1278                 }
1279         }
1280
1281         if (likely(status & AG71XX_INT_POLL)) {
1282                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1283                 DBG("%s: enable polling mode\n", dev->name);
1284                 napi_schedule(&ag->napi);
1285         }
1286
1287         ag71xx_debugfs_update_int_stats(ag, status);
1288
1289         return IRQ_HANDLED;
1290 }
1291
1292 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1293 {
1294         struct ag71xx *ag = netdev_priv(dev);
1295
1296         dev->mtu = new_mtu;
1297         ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1298                   ag71xx_max_frame_len(dev->mtu));
1299
1300         return 0;
1301 }
1302
1303 static const struct net_device_ops ag71xx_netdev_ops = {
1304         .ndo_open               = ag71xx_open,
1305         .ndo_stop               = ag71xx_stop,
1306         .ndo_start_xmit         = ag71xx_hard_start_xmit,
1307         .ndo_do_ioctl           = ag71xx_do_ioctl,
1308         .ndo_tx_timeout         = ag71xx_tx_timeout,
1309         .ndo_change_mtu         = ag71xx_change_mtu,
1310         .ndo_set_mac_address    = eth_mac_addr,
1311         .ndo_validate_addr      = eth_validate_addr,
1312 };
1313
1314 static int ag71xx_probe(struct platform_device *pdev)
1315 {
1316         struct device_node *np = pdev->dev.of_node;
1317         struct net_device *dev;
1318         struct resource *res;
1319         struct ag71xx *ag;
1320         const void *mac_addr;
1321         u32 max_frame_len;
1322         int tx_size, err;
1323
1324         if (!np)
1325                 return -ENODEV;
1326
1327         dev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1328         if (!dev)
1329                 return -ENOMEM;
1330
1331         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1332         if (!res)
1333                 return -EINVAL;
1334
1335         err = ag71xx_setup_gmac(np);
1336         if (err)
1337                 return err;
1338
1339         SET_NETDEV_DEV(dev, &pdev->dev);
1340
1341         ag = netdev_priv(dev);
1342         ag->pdev = pdev;
1343         ag->dev = dev;
1344         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1345                                         AG71XX_DEFAULT_MSG_ENABLE);
1346         spin_lock_init(&ag->lock);
1347
1348         ag->mac_reset = devm_reset_control_get_exclusive(&pdev->dev, "mac");
1349         if (IS_ERR(ag->mac_reset)) {
1350                 dev_err(&pdev->dev, "missing mac reset\n");
1351                 return PTR_ERR(ag->mac_reset);
1352         }
1353
1354         ag->mdio_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "mdio");
1355
1356         if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1357                 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1358                     of_device_is_compatible(np, "qca,ar7100-eth")) {
1359                         ag->fifodata[0] = 0x0fff0000;
1360                         ag->fifodata[1] = 0x00001fff;
1361                 } else {
1362                         ag->fifodata[0] = 0x0010ffff;
1363                         ag->fifodata[1] = 0x015500aa;
1364                         ag->fifodata[2] = 0x01f00140;
1365                 }
1366                 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1367                         ag->fifodata[2] = 0x00780fff;
1368                 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1369                         ag->fifodata[2] = 0x008001ff;
1370         }
1371
1372         if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1373                 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1374
1375         if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1376                 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1377
1378         ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1379         if (IS_ERR(ag->pllregmap)) {
1380                 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1381                 ag->pllregmap = NULL;
1382         }
1383
1384         ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1385                                             res->end - res->start + 1);
1386         if (!ag->mac_base)
1387                 return -ENOMEM;
1388
1389         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1390         if (res) {
1391                 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1392                                             res->end - res->start + 1);
1393                 if (!ag->mii_base)
1394                         return -ENOMEM;
1395         }
1396
1397         dev->irq = platform_get_irq(pdev, 0);
1398         err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1399                                0x0, dev_name(&pdev->dev), dev);
1400         if (err) {
1401                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1402                 return err;
1403         }
1404
1405         dev->netdev_ops = &ag71xx_netdev_ops;
1406         dev->ethtool_ops = &ag71xx_ethtool_ops;
1407
1408         INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1409
1410 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
1411         init_timer(&ag->oom_timer);
1412         ag->oom_timer.data = (unsigned long) dev;
1413         ag->oom_timer.function = ag71xx_oom_timer_handler;
1414 #else
1415         timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
1416 #endif
1417
1418         tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1419         ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1420
1421         if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1422             of_device_is_compatible(np, "qca,qca9530-eth") ||
1423             of_device_is_compatible(np, "qca,qca9550-eth") ||
1424             of_device_is_compatible(np, "qca,qca9560-eth"))
1425                 ag->desc_pktlen_mask = SZ_16K - 1;
1426         else
1427                 ag->desc_pktlen_mask = SZ_4K - 1;
1428
1429         if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1430             !of_device_is_compatible(np, "qca,qca9550-eth") &&
1431             !of_device_is_compatible(np, "qca,qca9560-eth"))
1432                 max_frame_len = ag->desc_pktlen_mask;
1433         else
1434                 max_frame_len = 1540;
1435
1436         dev->min_mtu = 68;
1437         dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1438
1439         if (of_device_is_compatible(np, "qca,ar7240-eth"))
1440                 ag->tx_hang_workaround = 1;
1441
1442         ag->rx_buf_offset = NET_SKB_PAD;
1443         if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1444             !of_device_is_compatible(np, "qca,ar9130-eth"))
1445                 ag->rx_buf_offset += NET_IP_ALIGN;
1446
1447         if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1448                 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1449                 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1450         }
1451         ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1452
1453         ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1454                                             sizeof(struct ag71xx_desc),
1455                                             &ag->stop_desc_dma, GFP_KERNEL);
1456         if (!ag->stop_desc)
1457                 return -ENOMEM;
1458
1459         ag->stop_desc->data = 0;
1460         ag->stop_desc->ctrl = 0;
1461         ag->stop_desc->next = (u32) ag->stop_desc_dma;
1462
1463         mac_addr = of_get_mac_address(np);
1464         if (mac_addr)
1465                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1466         if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1467                 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1468                 eth_random_addr(dev->dev_addr);
1469         }
1470
1471         ag->phy_if_mode = of_get_phy_mode(np);
1472         if (ag->phy_if_mode < 0) {
1473                 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1474                 return ag->phy_if_mode;
1475         }
1476
1477         if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1478                 ag->mac_idx = -1;
1479         if (ag->mii_base)
1480                 switch (ag->mac_idx) {
1481                 case 0:
1482                         ath79_mii0_ctrl_set_if(ag);
1483                         break;
1484                 case 1:
1485                         ath79_mii1_ctrl_set_if(ag);
1486                         break;
1487                 default:
1488                         break;
1489                 }
1490
1491         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1492
1493         ag71xx_dump_regs(ag);
1494
1495         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1496
1497         ag71xx_hw_init(ag);
1498
1499         ag71xx_dump_regs(ag);
1500
1501         /*
1502          * populate current node to register mdio-bus as a subdevice.
1503          * the mdio bus works independently on ar7241 and later chips
1504          * and we need to load mdio1 before gmac0, which can be done
1505          * by adding a "simple-mfd" compatible to gmac node. The
1506          * following code checks OF_POPULATED_BUS flag before populating
1507          * to avoid duplicated population.
1508          */
1509         if (!of_node_check_flag(np, OF_POPULATED_BUS)) {
1510                 err = of_platform_populate(np, NULL, NULL, &pdev->dev);
1511                 if (err)
1512                         return err;
1513         }
1514
1515         err = ag71xx_phy_connect(ag);
1516         if (err)
1517                 return err;
1518
1519         err = ag71xx_debugfs_init(ag);
1520         if (err)
1521                 goto err_phy_disconnect;
1522
1523         platform_set_drvdata(pdev, dev);
1524
1525         err = register_netdev(dev);
1526         if (err) {
1527                 dev_err(&pdev->dev, "unable to register net device\n");
1528                 platform_set_drvdata(pdev, NULL);
1529                 ag71xx_debugfs_exit(ag);
1530                 goto err_phy_disconnect;
1531         }
1532
1533         pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1534                 dev->name, (unsigned long) ag->mac_base, dev->irq,
1535                 phy_modes(ag->phy_if_mode));
1536
1537         return 0;
1538
1539 err_phy_disconnect:
1540         ag71xx_phy_disconnect(ag);
1541         return err;
1542 }
1543
1544 static int ag71xx_remove(struct platform_device *pdev)
1545 {
1546         struct net_device *dev = platform_get_drvdata(pdev);
1547         struct ag71xx *ag;
1548
1549         if (!dev)
1550                 return 0;
1551
1552         ag = netdev_priv(dev);
1553         ag71xx_debugfs_exit(ag);
1554         ag71xx_phy_disconnect(ag);
1555         unregister_netdev(dev);
1556         platform_set_drvdata(pdev, NULL);
1557         return 0;
1558 }
1559
1560 static const struct of_device_id ag71xx_match[] = {
1561         { .compatible = "qca,ar7100-eth" },
1562         { .compatible = "qca,ar7240-eth" },
1563         { .compatible = "qca,ar7241-eth" },
1564         { .compatible = "qca,ar7242-eth" },
1565         { .compatible = "qca,ar9130-eth" },
1566         { .compatible = "qca,ar9330-eth" },
1567         { .compatible = "qca,ar9340-eth" },
1568         { .compatible = "qca,qca9530-eth" },
1569         { .compatible = "qca,qca9550-eth" },
1570         { .compatible = "qca,qca9560-eth" },
1571         {}
1572 };
1573
1574 static struct platform_driver ag71xx_driver = {
1575         .probe          = ag71xx_probe,
1576         .remove         = ag71xx_remove,
1577         .driver = {
1578                 .name   = AG71XX_DRV_NAME,
1579                 .of_match_table = ag71xx_match,
1580         }
1581 };
1582
1583 static int __init ag71xx_module_init(void)
1584 {
1585         int ret;
1586
1587         ret = ag71xx_debugfs_root_init();
1588         if (ret)
1589                 goto err_out;
1590
1591         ret = platform_driver_register(&ag71xx_driver);
1592         if (ret)
1593                 goto err_debugfs_exit;
1594
1595         return 0;
1596
1597 err_debugfs_exit:
1598         ag71xx_debugfs_root_exit();
1599 err_out:
1600         return ret;
1601 }
1602
1603 static void __exit ag71xx_module_exit(void)
1604 {
1605         platform_driver_unregister(&ag71xx_driver);
1606         ag71xx_debugfs_root_exit();
1607 }
1608
1609 module_init(ag71xx_module_init);
1610 module_exit(ag71xx_module_exit);
1611
1612 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1613 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1614 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1615 MODULE_LICENSE("GPL v2");
1616 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);