1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
6 compatible = "qca,qca9560";
17 compatible = "mips,mips74Kc";
18 clocks = <&pll ATH79_CLK_CPU>;
24 compatible = "fixed-clock";
26 clock-output-names = "ref";
27 clock-frequency = <25000000>;
32 ddr_ctrl: memory-controller@18000000 {
33 compatible = "qca,qca9560-ddr-controller",
34 "qca,ar7240-ddr-controller";
35 reg = <0x18000000 0x100>;
37 #qca,ddr-wb-channel-cells = <1>;
41 compatible = "ns16550a";
42 reg = <0x18020000 0x20>;
46 clocks = <&pll ATH79_CLK_REF>;
57 compatible = "qca,qca9560-gpio",
59 reg = <0x18040000 0x28>;
68 #interrupt-cells = <2>;
71 pinmux: pinmux@1804002c {
72 compatible = "pinctrl-single";
74 reg = <0x1804002c 0x44>;
78 pinctrl-single,bit-per-mux;
79 pinctrl-single,register-width = <32>;
80 pinctrl-single,function-mask = <0x1>;
83 jtag_disable_pins: pinmux_jtag_disable_pins {
84 pinctrl-single,bits = <0x40 0x2 0x2>;
88 pll: pll-controller@18050000 {
89 compatible = "qca,qca9560-pll", "syscon";
90 reg = <0x18050000 0x50>;
93 clock-output-names = "cpu", "ddr", "ahb";
99 compatible = "qca,ar7130-wdt";
100 reg = <0x18060008 0x8>;
104 clocks = <&pll ATH79_CLK_AHB>;
108 rst: reset-controller@1806001c {
109 compatible = "qca,qca9560-reset",
111 reg = <0x1806001c 0x4>;
114 interrupt-parent = <&cpuintc>;
116 intc3: interrupt-controller {
117 compatible = "qca,ar9340-intc";
119 interrupt-parent = <&cpuintc>;
122 interrupt-controller;
123 #interrupt-cells = <1>;
125 qca,int-status-addr = <0xac>;
126 qca,pending-bits = <0x1f000>, /* pcie rc */
127 <0x1000000>, /* usb1 */
128 <0x10000000>; /* usb2 */
132 rst2: reset-controller@180600c0 {
133 compatible = "qca,qca9560-reset",
136 reg = <0x180600c0 0x4>;
142 gmac: gmac@18070000 {
143 compatible = "qca,qca9560-gmac";
144 reg = <0x18070000 0x64>;
147 wmac: wmac@18100000 {
148 compatible = "qca,qca9560-wmac";
149 reg = <0x18100000 0x10000>;
151 interrupt-parent = <&cpuintc>;
157 pcie: pcie-controller@18250000 {
158 compatible = "qcom,ar7240-pci";
159 #address-cells = <3>;
161 bus-range = <0x0 0x0>;
162 reg = <0x18250000 0x1000>, /* CRP */
163 <0x18280000 0x100>, /* CTRL */
164 <0x16000000 0x1000>; /* CFG */
165 reg-names = "crp_base", "ctrl_base", "cfg_base";
166 ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
167 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
168 interrupt-parent = <&intc3>;
171 resets = <&rst 6>, <&rst 7>;
172 reset-names = "hc", "phy";
174 interrupt-controller;
175 #interrupt-cells = <1>;
177 interrupt-map-mask = <0 0 0 1>;
178 interrupt-map = <0 0 0 0 &pcie 0>;
183 compatible = "generic-ehci";
184 reg = <0x1b000000 0x1d8>;
186 interrupt-parent = <&intc3>;
190 reset-names = "usb-host";
192 has-transaction-translator;
193 caps-offset = <0x100>;
195 phy-names = "usb-phy0";
202 compatible = "generic-ehci";
203 reg = <0x1b400000 0x1d8>;
205 interrupt-parent = <&intc3>;
209 reset-names = "usb-host";
211 has-transaction-translator;
212 caps-offset = <0x100>;
214 phy-names = "usb-phy1";
221 compatible = "qca,ar934x-spi";
222 reg = <0x1f000000 0x1c>;
224 clocks = <&pll ATH79_CLK_AHB>;
228 #address-cells = <1>;
234 compatible = "qca,qca9560-usb-phy", "qca,ar7200-usb-phy";
236 reset-names = "usb-phy", "usb-suspend-override";
237 resets = <&rst 4>, <&rst 3>;
245 compatible = "qca,qca9560-usb-phy", "qca,ar7200-usb-phy";
247 reset-names = "usb-phy", "usb-suspend-override";
248 resets = <&rst2 4>, <&rst2 3>;
258 reset-names = "mdio";
262 compatible = "qca,qca9560-eth", "syscon";
264 pll-data = <0x03000000 0x00000101 0x00001919>;
265 pll-reg = <0 0x48 0>;
275 reset-names = "mdio";
278 builtin_switch: switch0@1f {
279 compatible = "qca,ar8229";
282 reset-names = "switch";
285 qca,mib-poll-interval = <500>;
288 #address-cells = <1>;
291 swphy0: ethernet-phy@0 {
296 swphy4: ethernet-phy@4 {
305 compatible = "qca,qca9560-eth", "syscon";