ath79: qca95xx: add new intc2, correct intc3 and add second pcie on qca9557
[oweals/openwrt.git] / target / linux / ath79 / dts / qca9558_openmesh_om5p-ac-v2.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 #include "qca9557.dtsi"
8
9 / {
10         compatible = "openmesh,om5p-ac-v2", "qca,qca9557";
11         model = "OpenMesh OM5P-AC V2";
12
13         memory@0 {
14                 device_type = "memory";
15                 reg = <0x0 0x8000000>;
16         };
17
18         extosc: ref {
19                 compatible = "fixed-clock";
20                 #clock-cells = <0>;
21                 clock-output-names = "ref";
22                 clock-frequency = <40000000>;
23         };
24
25         leds {
26                 compatible = "gpio-leds";
27
28                 power {
29                         label = "om5pac:blue:power";
30                         gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
31                         default-state = "off";
32                 };
33
34                 wifi_green {
35                         label = "om5pac:green:wifi";
36                         gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
37                         default-state = "off";
38                 };
39
40                 wifi_yellow {
41                         label = "om5pac:yellow:wifi";
42                         gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
43                         default-state = "off";
44                 };
45
46                 wifi_red {
47                         label = "om5pac:red:wifi";
48                         gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
49                         default-state = "off";
50                 };
51         };
52
53         keys {
54                 compatible = "gpio-keys-polled";
55                 #address-cells = <1>;
56                 #size-cells = <0>;
57                 poll-interval = <100>;
58
59                 button@0 {
60                         label = "reset";
61                         linux,code = <KEY_RESTART>;
62                         gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
63                 };
64         };
65
66         gpio-export {
67                 compatible = "gpio-export";
68                 #size-cells = <0>;
69
70                 gpio_pa_dcdc {
71                         gpio-export,name = "om5pac:pa_dcdc";
72                         gpio-export,output = <1>;
73                         gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
74                 };
75                 gpio_pa_high {
76                         gpio-export,name = "om5pac:pa_high";
77                         gpio-export,output = <1>;
78                         gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
79                 };
80         };
81 };
82
83 &pinmux {
84         pinmux_pa_dcdc_pins {
85                 pinctrl-single,bits = <0x0 0xff00 0x0>;
86         };
87
88         pinmux_pa_high_pins {
89                 pinctrl-single,bits = <0x10 0xff 0x0>;
90         };
91 };
92
93 &pcie0 {
94         status = "okay";
95 };
96
97 &uart {
98         status = "okay";
99 };
100
101 &pll {
102         clocks = <&extosc>;
103 };
104
105 &spi {
106         status = "okay";
107         num-cs = <1>;
108
109         flash@0 {
110                 #address-cells = <1>;
111                 #size-cells = <1>;
112                 compatible = "mx25l12805d";
113                 reg = <0>;
114                 spi-max-frequency = <25000000>;
115
116                 partitions {
117                         compatible = "fixed-partitions";
118                         #address-cells = <1>;
119                         #size-cells = <1>;
120
121                         partition@0 {
122                                 label = "u-boot";
123                                 reg = <0x000000 0x040000>;
124                                 read-only;
125                         };
126
127                         partition@1 {
128                                 label = "u-boot-env";
129                                 reg = <0x040000 0x010000>;
130                         };
131
132                         partition@2 {
133                                 label = "firmware";
134                                 reg = <0x850000 0x7a0000>;
135                         };
136
137                         partition@3 {
138                                 label = "ART";
139                                 reg = <0xff0000 0x010000>;
140                                 read-only;
141                         };
142                 };
143         };
144 };
145
146 &mdio0 {
147         status = "okay";
148
149         phy4: ethernet-phy@4 {
150                 reg = <4>;
151                 phy-mode = "rgmii-id";
152         };
153 };
154
155 &mdio1 {
156         status = "okay";
157
158         phy1: ethernet-phy@1 {
159                 reg = <1>;
160                 phy-mode = "sgmii";
161         };
162 };
163
164 &eth0 {
165         status = "okay";
166
167         phy-handle = <&phy4>;
168         phy-mode = "rgmii";
169 };
170
171 &eth1 {
172         status = "okay";
173
174         phy-handle = <&phy1>;
175         phy-mode = "sgmii";
176 };