target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /dts-v1/;
   3
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6
   7 #include "qca955x.dtsi"
   8
   9 / {
  10         compatible = "openmesh,om5p-ac-v2", "qca,qca9558";
  11         model = "OpenMesh OM5P-AC V2";
  12
  13         extosc: ref {
  14                 compatible = "fixed-clock";
  15                 #clock-cells = <0>;
  16                 clock-output-names = "ref";
  17                 clock-frequency = <40000000>;
  18         };
  19
  20         leds {
  21                 compatible = "gpio-leds";
  22
  23                 power {
  24                         label = "om5pac:blue:power";
  25                         gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  26                 };
  27
  28                 wifi_green {
  29                         label = "om5pac:green:wifi";
  30                         gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
  31                 };
  32
  33                 wifi_yellow {
  34                         label = "om5pac:yellow:wifi";
  35                         gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
  36                 };
  37
  38                 wifi_red {
  39                         label = "om5pac:red:wifi";
  40                         gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
  41                 };
  42         };
  43
  44         keys {
  45                 compatible = "gpio-keys";
  46
  47                 reset {
  48                         label = "reset";
  49                         linux,code = <KEY_RESTART>;
  50                         gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
  51                 };
  52         };
  53
  54         gpio-export {
  55                 compatible = "gpio-export";
  56                 #size-cells = <0>;
  57
  58                 gpio_pa_dcdc {
  59                         gpio-export,name = "om5pac:pa_dcdc";
  60                         gpio-export,output = <1>;
  61                         gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
  62                 };
  63                 gpio_pa_high {
  64                         gpio-export,name = "om5pac:pa_high";
  65                         gpio-export,output = <1>;
  66                         gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
  67                 };
  68         };
  69 };
  70
  71 &pinmux {
  72         pinmux_pa_dcdc_pins {
  73                 pinctrl-single,bits = <0x0 0xff00 0x0>;
  74         };
  75
  76         pinmux_pa_high_pins {
  77                 pinctrl-single,bits = <0x10 0xff 0x0>;
  78         };
  79 };
  80
  81 &pcie0 {
  82         status = "okay";
  83 };
  84
  85 &uart {
  86         status = "okay";
  87 };
  88
  89 &pll {
  90         clocks = <&extosc>;
  91 };
  92
  93 &spi {
  94         status = "okay";
  95         num-cs = <1>;
  96
  97         flash@0 {
  98                 compatible = "jedec,spi-nor";
  99                 reg = <0>;
 100                 spi-max-frequency = <25000000>;
 101
 102                 partitions {
 103                         compatible = "fixed-partitions";
 104                         #address-cells = <1>;
 105                         #size-cells = <1>;
 106
 107                         partition@0 {
 108                                 label = "u-boot";
 109                                 reg = <0x000000 0x040000>;
 110                                 read-only;
 111                         };
 112
 113                         partition@1 {
 114                                 label = "u-boot-env";
 115                                 reg = <0x040000 0x010000>;
 116                         };
 117
 118                         partition@2 {
 119                                 compatible = "denx,uimage";
 120                                 label = "firmware";
 121                                 reg = <0x850000 0x7a0000>;
 122                         };
 123
 124                         partition@3 {
 125                                 label = "art";
 126                                 reg = <0xff0000 0x010000>;
 127                                 read-only;
 128                         };
 129                 };
 130         };
 131 };
 132
 133 &mdio0 {
 134         status = "okay";
 135
 136         phy4: ethernet-phy@4 {
 137                 reg = <4>;
 138                 phy-mode = "rgmii-id";
 139         };
 140 };
 141
 142 &mdio1 {
 143         status = "okay";
 144
 145         phy1: ethernet-phy@1 {
 146                 reg = <1>;
 147                 phy-mode = "sgmii";
 148         };
 149 };
 150
 151 &eth0 {
 152         status = "okay";
 153
 154         pll-data = <0x82000101 0x80000101 0x80001313>;
 155
 156         phy-handle = <&phy4>;
 157         phy-mode = "rgmii";
 158 };
 159
 160 &eth1 {
 161         status = "okay";
 162
 163         pll-data = <0x03000101 0x80000101 0x80001313>;
 164
 165         phy-handle = <&phy1>;
 166         phy-mode = "sgmii";
 167 };