target/linux/ath79/dts/qca9557.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 #include <dt-bindings/clock/ath79-clk.h>
   3 #include "ath79.dtsi"
   4
   5 / {
   6         compatible = "qca,qca9557";
   7
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14
  15                 cpu@0 {
  16                         device_type = "cpu";
  17                         compatible = "mips,mips24Kc";
  18                         clocks = <&pll ATH79_CLK_CPU>;
  19                         reg = <0>;
  20                 };
  21         };
  22
  23         ahb {
  24                 apb {
  25                         ddr_ctrl: memory-controller@18000000 {
  26                                 compatible = "qca,ar9557-ddr-controller",
  27                                                 "qca,ar7240-ddr-controller";
  28                                 reg = <0x18000000 0x100>;
  29
  30                                 #qca,ddr-wb-channel-cells = <1>;
  31                         };
  32
  33                         uart: uart@18020000 {
  34                                 compatible = "ns16550a";
  35                                 reg = <0x18020000 0x20>;
  36
  37                                 interrupts = <3>;
  38
  39                                 clocks = <&pll ATH79_CLK_REF>;
  40                                 clock-names = "uart";
  41
  42                                 reg-io-width = <4>;
  43                                 reg-shift = <2>;
  44                                 no-loopback-test;
  45
  46                                 status = "disabled";
  47                         };
  48
  49                         gpio: gpio@18040000 {
  50                                 compatible = "qca,ar9557-gpio",
  51                                                 "qca,ar9340-gpio";
  52                                 reg = <0x18040000 0x28>;
  53
  54                                 interrupts = <2>;
  55                                 ngpios = <24>;
  56
  57                                 gpio-controller;
  58                                 #gpio-cells = <2>;
  59
  60                                 interrupt-controller;
  61                                 #interrupt-cells = <2>;
  62                         };
  63
  64                         pinmux: pinmux@1804002c {
  65                                 compatible = "pinctrl-single";
  66
  67                                 reg = <0x1804002c 0x40>;
  68
  69                                 #size-cells = <0>;
  70
  71                                 pinctrl-single,bit-per-mux;
  72                                 pinctrl-single,register-width = <32>;
  73                                 pinctrl-single,function-mask = <0x1>;
  74                                 #pinctrl-cells = <2>;
  75
  76                                 jtag_disable_pins: pinmux_jtag_disable_pins {
  77                                         pinctrl-single,bits = <0x40 0x2  0x2>;
  78                                 };
  79                         };
  80
  81                         pll: pll-controller@18050000 {
  82                                 compatible = "qca,ar9557-pll",
  83                                                 "qca,qca9550-pll";
  84                                 reg = <0x18050000 0x20>;
  85
  86                                 #clock-cells = <1>;
  87                                 clock-output-names = "cpu", "ddr", "ahb";
  88                         };
  89
  90                         wdt: wdt@18060008 {
  91                                 compatible = "qca,ar7130-wdt";
  92                                 reg = <0x18060008 0x8>;
  93
  94                                 interrupts = <4>;
  95
  96                                 clocks = <&pll ATH79_CLK_AHB>;
  97                                 clock-names = "wdt";
  98                         };
  99
 100                         rst: reset-controller@1806001c {
 101                                 compatible = "qca,ar9557-reset",
 102                                                 "qca,ar7100-reset",
 103                                                  "simple-bus";
 104                                 reg = <0x1806001c 0x4>;
 105
 106                                 #reset-cells = <1>;
 107                                 interrupt-parent = <&cpuintc>;
 108
 109                                 intc2: interrupt-controller@2 {
 110                                         compatible = "qcom,qca9556-intc";
 111
 112                                         interrupts = <2>;
 113
 114                                         interrupt-controller;
 115                                         #interrupt-cells = <1>;
 116
 117                                         qcom,pending-bits = <0x1f0>,    /* pcie rc1 */
 118                                                             <0xf>;      /* wmac */
 119                                 };
 120
 121                                 intc3: interrupt-controller@3 {
 122                                         compatible = "qcom,qca9556-intc";
 123
 124                                         interrupts = <3>;
 125
 126                                         interrupt-controller;
 127                                         #interrupt-cells = <1>;
 128
 129                                         qcom,pending-bits = <0x1f000>,          /* pcie rc2 */
 130                                                             <0x1000000>,        /* usb1 */
 131                                                             <0x10000000>;       /* usb2 */
 132                                 };
 133                         };
 134
 135                         pcie0: pcie-controller@180c0000 {
 136                                 compatible = "qcom,ar7240-pci";
 137                                 #address-cells = <3>;
 138                                 #size-cells = <2>;
 139                                 bus-range = <0x0 0x0>;
 140                                 reg = <0x180c0000 0x1000>, /* CRP */
 141                                       <0x180f0000 0x100>,  /* CTRL */
 142                                       <0x14000000 0x1000>; /* CFG */
 143                                 reg-names = "crp_base", "ctrl_base", "cfg_base";
 144                                 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000        /* pci memory */
 145                                           0x1000000 0 0x00000000 0x0000000 0 0x000001>;         /* io space */
 146                                 interrupt-parent = <&intc2>;
 147                                 interrupts = <0>;
 148
 149                                 interrupt-controller;
 150                                 #interrupt-cells = <1>;
 151
 152                                 interrupt-map-mask = <0 0 0 1>;
 153                                 interrupt-map = <0 0 0 0 &pcie0 0>;
 154                                 status = "disabled";
 155                         };
 156                 };
 157
 158                 spi: spi@1f000000 {
 159                         compatible = "qca,ar9557-spi", "qca,ar7100-spi";
 160                         reg = <0x1f000000 0x10>;
 161
 162                         clocks = <&pll ATH79_CLK_AHB>;
 163                         clock-names = "ahb";
 164
 165                         status = "disabled";
 166
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                 };
 170         };
 171 };
 172
 173 &mdio0 {
 174         resets = <&rst 22>;
 175         reset-names = "mdio";
 176 };
 177
 178 &eth0 {
 179         compatible = "qca,qca9550-eth", "syscon";
 180
 181         pll-data = <0x82000101 0x80000101 0x80001313>;
 182         phy-mode = "rgmii";
 183
 184         resets = <&rst 9>;
 185         reset-names = "mac";
 186 };
 187
 188 &mdio1 {
 189         resets = <&rst 23>;
 190         reset-names = "mdio";
 191 };
 192
 193 &eth1 {
 194         compatible = "qca,qca9550-eth", "syscon";
 195
 196         pll-data = <0x82000101 0x80000101 0x80001313>;
 197         phy-mode = "sgmii";
 198
 199         resets = <&rst 13>;
 200         reset-names = "mac";
 201 };