1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
6 compatible = "qca,qca9533";
12 bootargs = "console=ttyS0,115200n8";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
28 compatible = "fixed-clock";
30 clock-output-names = "ref";
31 clock-frequency = <25000000>;
36 ddr_ctrl: memory-controller@18000000 {
37 compatible = "qca,ar9530-ddr-controller",
38 "qca,ar7240-ddr-controller";
39 reg = <0x18000000 0x128>;
41 #qca,ddr-wb-channel-cells = <1>;
45 compatible = "ns16550a";
46 reg = <0x18020000 0x20>;
50 clocks = <&pll ATH79_CLK_REF>;
60 usb_phy: usb-phy@18030000 {
61 compatible = "qca,ar7200-usb-phy";
62 reg = <0x18030000 0x100>;
65 reset-names = "usb-phy", "usb-suspend-override";
66 resets = <&rst 4>, <&rst 3>;
72 compatible = "qca,ar9530-gpio",
74 reg = <0x18040000 0x28>;
83 #interrupt-cells = <2>;
86 pinmux: pinmux@1804002c {
87 compatible = "pinctrl-single";
89 reg = <0x1804002c 0x48>;
93 pinctrl-single,bit-per-mux;
94 pinctrl-single,register-width = <32>;
95 pinctrl-single,function-mask = <0x1>;
98 jtag_disable_pins: pinmux_jtag_disable_pins {
99 pinctrl-single,bits = <0x40 0x2 0x2>;
103 pll: pll-controller@18050000 {
104 compatible = "qca,qca9530-pll", "syscon";
105 reg = <0x18050000 0x48>;
108 clock-output-names = "cpu", "ddr", "ahb";
113 compatible = "qca,qca9530-wdt", "qca,ar7130-wdt";
114 reg = <0x18060008 0x8>;
118 clocks = <&pll ATH79_CLK_AHB>;
122 rst: reset-controller@1806001c {
123 compatible = "qca,qca9530-reset",
125 reg = <0x1806001c 0xac>;
129 intc2: interrupt-controller {
130 compatible = "qca,ar9340-intc";
132 interrupt-parent = <&cpuintc>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
138 qca,int-status-addr = <0xac>;
139 qca,pending-bits = <0xf>, /* wmac */
140 <0x1f0>; /* pcie rc1 */
142 qca,ddr-wb-channel-interrupts = <0>, <1>;
143 qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;
147 pcie0: pcie-controller@180c0000 {
148 compatible = "qcom,ar7240-pci";
149 #address-cells = <3>;
151 bus-range = <0x0 0x0>;
152 reg = <0x180c0000 0x1000>, /* CRP */
153 <0x180f0000 0x100>, /* CTRL */
154 <0x14000000 0x1000>; /* CFG */
155 reg-names = "crp_base", "ctrl_base", "cfg_base";
156 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
157 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
158 interrupt-parent = <&intc2>;
161 interrupt-controller;
162 #interrupt-cells = <1>;
164 interrupt-map-mask = <0 0 0 1>;
165 interrupt-map = <0 0 0 0 &pcie0 0>;
169 gmac: gmac@18070000 {
170 compatible = "qca,ar9330-gmac";
171 reg = <0x18070000 0x4>;
174 wmac: wmac@18100000 {
175 compatible = "qca,qca9530-wmac";
176 reg = <0x18100000 0x230000>;
178 interrupt-parent = <&intc2>;
186 compatible = "generic-ehci";
187 reg = <0x1b000000 0x1000>;
191 reset-names = "usb-host";
194 has-transaction-translator;
195 caps-offset = <0x100>;
197 phy-names = "usb-phy";
204 compatible = "qca,ar9530-spi", "qca,ar7100-spi";
205 reg = <0x1f000000 0x10>;
207 clocks = <&pll ATH79_CLK_AHB>;
212 #address-cells = <1>;
221 qca,ddr-wb-channel-interrupts = <3>, <4>, <5>;
222 qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,
227 compatible = "qca,qca9530-eth", "syscon";
228 pll-data = <0x82000101 0x80000101 0x80001313>;
229 reg = <0x19000000 0x200
231 pll-reg = <0x4 0x2c 17>;
244 reset-names = "mdio";
247 builtin_switch: switch0@1f {
248 compatible = "qca,ar8229-builtin";
252 reset-names = "switch";
257 #address-cells = <1>;
260 swphy0: ethernet-phy@0 {
265 swphy4: ethernet-phy@4 {
276 compatible = "qca,qca9530-eth", "syscon", "simple-mfd";