1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/clock/ath79-clk.h>
8 compatible = "qca,ar9340";
14 bootargs = "console=ttyS0,115200";
23 compatible = "mips,mips74Kc";
24 clocks = <&pll ATH79_CLK_CPU>;
36 compatible = "fixed-clock";
37 clock-output-names = "ref";
42 compatible = "simple-bus";
49 compatible = "simple-bus";
55 ddr_ctrl: memory-controller@18000000 {
56 compatible = "qca,ar9340-ddr-controller",
57 "qca,ar7240-ddr-controller";
58 reg = <0x18000000 0x12c>;
60 #qca,ddr-wb-channel-cells = <1>;
64 compatible = "ns16550a";
65 reg = <0x18020000 0x2c>;
69 clocks = <&pll ATH79_CLK_REF>;
80 compatible = "qca,ar9340-gpio";
81 reg = <0x18040000 0x2c>;
90 #interrupt-cells = <2>;
93 pinmux: pinmux@1804002c {
94 compatible = "pinctrl-single";
96 reg = <0x1804002c 0x44>;
100 pinctrl-single,bit-per-mux;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0x1>;
103 #pinctrl-cells = <2>;
105 jtag_disable_pins: pinmux_jtag_disable_pins {
106 pinctrl-single,bits = <0x40 0x2 0x2>;
110 pll: pll-controller@18050000 {
111 compatible = "qca,ar9340-pll", "syscon";
112 reg = <0x18050000 0x4c>;
117 clock-output-names = "cpu", "ddr", "ahb";
121 compatible = "qca,ar9340-wdt", "qca,ar7130-wdt";
122 reg = <0x18060008 0x8>;
126 clocks = <&pll ATH79_CLK_AHB>;
130 rst: reset-controller@1806001c {
131 compatible = "qca,ar9340-reset", "qca,ar7100-reset";
132 reg = <0x1806001c 0x4>;
137 hs_uart: uart@18500000 {
138 compatible = "qca,ar9330-uart";
139 reg = <0x18500000 0x14>;
142 interrupt-parent = <&miscintc>;
144 clocks = <&pll ATH79_CLK_UART1>;
145 clock-names = "uart";
151 nand: nand@1b000200 {
152 compatible = "qca,ar934x-nand";
153 reg = <0x1b000200 0xb8>;
156 interrupt-parent = <&miscintc>;
159 reset-names = "nand";
161 nand-ecc-mode = "hw";
163 #address-cells = <1>;
169 gmac: gmac@18070000 {
170 compatible = "qca,ar9340-gmac";
171 reg = <0x18070000 0x14>;
174 wmac: wmac@18100000 {
175 compatible = "qca,ar9340-wmac";
176 reg = <0x18100000 0x20000>;
182 compatible = "generic-ehci";
183 reg = <0x1b000000 0x1d8>;
187 reset-names = "usb-host";
189 has-transaction-translator;
190 caps-offset = <0x100>;
192 phy-names = "usb-phy";
199 compatible = "qca,ar934x-spi";
200 reg = <0x1f000000 0x1c>;
202 clocks = <&pll ATH79_CLK_AHB>;
204 #address-cells = <1>;
212 compatible = "qca,ar9340-usb-phy", "qca,ar7200-usb-phy";
214 reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
215 resets = <&rst 11>, <&rst 4>, <&rst 3>;
224 compatible = "qca,ar9340-mdio";
228 compatible = "qca,ar9340-eth", "syscon";
230 pll-data = <0x16000000 0x00000101 0x00001616>;
231 pll-reg = <0x4 0x2c 17>;
233 resets = <&rst 9>, <&rst 22>;
234 reset-names = "mac", "mdio";
235 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
236 clock-names = "eth", "mdio";
242 compatible = "qca,ar9340-mdio";
244 reset-names = "mdio";
247 builtin_switch: switch0@1f {
248 compatible = "qca,ar8229";
252 reset-names = "switch";
254 qca,mib-poll-interval = <500>;
258 #address-cells = <1>;
261 swphy0: ethernet-phy@0 {
266 swphy4: ethernet-phy@4 {
275 compatible = "qca,ar9340-eth", "syscon";
277 resets = <&rst 13>, <&rst 23>;
278 reset-names = "mac", "mdio";
279 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
280 clock-names = "eth", "mdio";