target/linux/ath79/dts/ar9344_wd_mynet-n750.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /dts-v1/;
   3
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6
   7 #include "ar9344.dtsi"
   8
   9 / {
  10         model = "Western Digital My Net N750";
  11         compatible = "wd,mynet-n750", "qca,ar9344";
  12
  13         chosen {
  14                 bootargs = "console=ttyS0,115200n8";
  15         };
  16
  17         aliases {
  18                 led-boot = &led_power;
  19                 led-failsafe = &led_power;
  20                 led-running = &led_power;
  21                 led-upgrade = &led_power;
  22         };
  23
  24         leds {
  25                 compatible = "gpio-leds";
  26
  27                 wifi {
  28                         label = "mynet-n750:blue:wireless";
  29                         gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
  30                 };
  31
  32                 internet {
  33                         label = "mynet-n750:blue:internet";
  34                         gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
  35                 };
  36
  37                 wps {
  38                         label = "mynet-n750:blue:wps";
  39                         gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
  40                 };
  41
  42                 led_power: power {
  43                         label = "mynet-n750:blue:power";
  44                         gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
  45                 };
  46         };
  47
  48         keys {
  49                 compatible = "gpio-keys";
  50
  51                 reset {
  52                         linux,code = <KEY_RESTART>;
  53                         gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  54                 };
  55
  56                 wps {
  57                         linux,code = <KEY_WPS_BUTTON>;
  58                         gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
  59                 };
  60         };
  61 };
  62
  63 &ref {
  64         clock-frequency = <40000000>;
  65 };
  66
  67 &uart {
  68         status = "okay";
  69 };
  70
  71 &gpio {
  72         status = "okay";
  73
  74         gpio_ext_lna0 {
  75                 gpio-hog;
  76                 gpios = <15 0>;
  77                 output-high;
  78                 line-name = "mynet-n750:ext:lna0";
  79         };
  80
  81         gpio_ext_lna1 {
  82                 gpio-hog;
  83                 gpios = <18 0>;
  84                 output-high;
  85                 line-name = "mynet-n750:ext:lna1";
  86         };
  87 };
  88
  89 &spi {
  90         status = "okay";
  91
  92         num-cs = <1>;
  93
  94         flash@0 {
  95                 compatible = "jedec,spi-nor";
  96                 reg = <0>;
  97                 spi-max-frequency = <25000000>;
  98
  99                 partitions {
 100                         compatible = "fixed-partitions";
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103
 104                         partition@0 {
 105                                 label = "bootloader";
 106                                 reg = <0x000000 0x40000>;
 107                                 read-only;
 108                         };
 109
 110                         partition@40000 {
 111                                 label = "bdcfg";
 112                                 reg = <0x040000 0x10000>;
 113                                 read-only;
 114                         };
 115
 116                         partition@50000 {
 117                                 label = "devdata";
 118                                 reg = <0x050000 0x10000>;
 119                                 read-only;
 120                         };
 121
 122                         partition@60000 {
 123                                 label = "devconf";
 124                                 reg = <0x060000 0x10000>;
 125                                 read-only;
 126                         };
 127
 128                         partition@70000 {
 129                                 compatible = "seama";
 130                                 label = "firmware";
 131                                 reg = <0x070000 0xf80000>;
 132                         };
 133
 134                         art: partition@ff0000 {
 135                                 label = "art";
 136                                 reg = <0xff0000 0x010000>;
 137                                 read-only;
 138                         };
 139                 };
 140         };
 141 };
 142
 143 &usb {
 144         #address-cells = <1>;
 145         #size-cells = <0>;
 146         status = "okay";
 147
 148         port@1 {
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151                 reg = <1>;
 152                 #trigger-source-cells = <0>;
 153
 154                 hub_port1: port@1 {
 155                         reg = <1>;
 156                         #trigger-source-cells = <0>;
 157                 };
 158
 159                 hub_port2: port@2 {
 160                         reg = <2>;
 161                         #trigger-source-cells = <0>;
 162                 };
 163         };
 164 };
 165
 166 &usb_phy {
 167         status = "okay";
 168 };
 169
 170 &pcie {
 171         status = "okay";
 172
 173         wifi@0,0 {
 174                 compatible = "pci168c,0033";
 175                 reg = <0x0000 0 0 0 0>;
 176                 qca,no-eeprom;
 177         };
 178 };
 179
 180 &wmac {
 181         status = "okay";
 182
 183         qca,no-eeprom;
 184 };
 185
 186 &mdio0 {
 187         status = "okay";
 188
 189         phy-mask = <0>;
 190
 191         switch0@1f {
 192                 compatible = "qca,ar8327";
 193                 reg = <0x1f>;
 194
 195                 qca,ar8327-initvals = <
 196                         0x04 0x07600000 /* PORT0 PAD MODE CTRL */
 197                         0x10 0x80000080 /* POWER_ON_STRIP */
 198                         0x50 0xc737c737 /* LED_CTRL0 */
 199                         0x54 0x00000000 /* LED_CTRL1 */
 200                         0x58 0x00000000 /* LED_CTRL2 */
 201                         0x5c 0x0030c300 /* LED_CTRL3 */
 202                         0x7c 0x0000007e /* PORT0_STATUS */
 203                         >;
 204         };
 205 };
 206
 207 &eth0 {
 208         status = "okay";
 209
 210         /* default for ar934x, except for 1000M */
 211         pll-data = <0x06000000 0x00000101 0x00001616>;
 212
 213         phy-mode = "rgmii";
 214         fixed-link {
 215                 speed = <1000>;
 216                 full-duplex;
 217         };
 218 };