target/linux/ath79/dts/ar9132.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/ath79-clk.h>
   3 #include "ath79.dtsi"
   4
   5 / {
   6         compatible = "qca,ar9132";
   7
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10
  11         chosen {
  12                 bootargs = "console=ttyS0,115200";
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips24Kc";
  22                         clocks = <&pll ATH79_CLK_CPU>;
  23                         reg = <0>;
  24                 };
  25         };
  26
  27         cpuintc: interrupt-controller {
  28                 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
  29
  30                 interrupt-controller;
  31                 #interrupt-cells = <1>;
  32
  33                 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
  34                 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
  35                                         <&ddr_ctrl 0>, <&ddr_ctrl 1>;
  36         };
  37
  38         ahb {
  39                 compatible = "simple-bus";
  40                 ranges;
  41
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44
  45                 interrupt-parent = <&cpuintc>;
  46
  47                 apb {
  48                         compatible = "simple-bus";
  49                         ranges;
  50
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53
  54                         interrupt-parent = <&miscintc>;
  55
  56                         ddr_ctrl: memory-controller@18000000 {
  57                                 compatible = "qca,ar9132-ddr-controller",
  58                                                 "qca,ar7240-ddr-controller";
  59                                 reg = <0x18000000 0x100>;
  60
  61                                 #qca,ddr-wb-channel-cells = <1>;
  62                         };
  63
  64                         uart: uart@18020000 {
  65                                 compatible = "ns8250";
  66                                 reg = <0x18020000 0x20>;
  67                                 interrupts = <3>;
  68
  69                                 clocks = <&pll ATH79_CLK_AHB>;
  70                                 clock-names = "uart";
  71
  72                                 reg-io-width = <4>;
  73                                 reg-shift = <2>;
  74                                 no-loopback-test;
  75
  76                                 status = "disabled";
  77                         };
  78
  79                         gpio: gpio@18040000 {
  80                                 compatible = "qca,ar9132-gpio",
  81                                                 "qca,ar7100-gpio";
  82                                 reg = <0x18040000 0x30>;
  83                                 interrupts = <2>;
  84
  85                                 ngpios = <22>;
  86
  87                                 gpio-controller;
  88                                 #gpio-cells = <2>;
  89
  90                                 interrupt-controller;
  91                                 #interrupt-cells = <2>;
  92                         };
  93
  94                         pll: pll-controller@18050000 {
  95                                 compatible = "qca,ar9132-pll",
  96                                                 "qca,ar9130-pll", "syscon";
  97                                 reg = <0x18050000 0x20>;
  98
  99                                 clock-names = "ref";
 100                                 /* The board must provides the ref clock */
 101
 102                                 #clock-cells = <1>;
 103                                 clock-output-names = "cpu", "ddr", "ahb";
 104                         };
 105
 106                         wdt: wdt@18060008 {
 107                                 compatible = "qca,ar7130-wdt";
 108                                 reg = <0x18060008 0x8>;
 109
 110                                 interrupts = <4>;
 111
 112                                 clocks = <&pll ATH79_CLK_AHB>;
 113                                 clock-names = "wdt";
 114                         };
 115
 116                         miscintc: interrupt-controller@18060010 {
 117                                 compatible = "qca,ar9132-misc-intc",
 118                                            "qca,ar7100-misc-intc";
 119                                 reg = <0x18060010 0x8>;
 120
 121                                 interrupt-parent = <&cpuintc>;
 122                                 interrupts = <6>;
 123
 124                                 interrupt-controller;
 125                                 #interrupt-cells = <1>;
 126                         };
 127
 128                         rst: reset-controller@1806001c {
 129                                 compatible = "qca,ar9132-reset",
 130                                                 "qca,ar7100-reset";
 131                                 reg = <0x1806001c 0x4>;
 132
 133                                 #reset-cells = <1>;
 134                         };
 135                 };
 136
 137                 usb: usb@1b000100 {
 138                         compatible = "qca,ar7100-ehci", "generic-ehci";
 139                         reg = <0x1b000100 0x100>;
 140
 141                         interrupts = <3>;
 142                         resets = <&rst 5>;
 143
 144                         has-transaction-translator;
 145
 146                         phy-names = "usb";
 147                         phys = <&usb_phy>;
 148
 149                         status = "disabled";
 150                 };
 151
 152                 spi: spi@1f000000 {
 153                         compatible = "qca,ar9132-spi", "qca,ar7100-spi";
 154                         reg = <0x1f000000 0x10>;
 155
 156                         clocks = <&pll ATH79_CLK_AHB>;
 157                         clock-names = "ahb";
 158
 159                         status = "disabled";
 160
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                 };
 164
 165                 wmac: wmac@180c0000 {
 166                         compatible = "qca,ar9130-wmac";
 167                         reg = <0x180c0000 0x230000>;
 168
 169                         interrupts = <2>;
 170
 171                         status = "disabled";
 172                 };
 173         };
 174
 175         usb_phy: usb-phy {
 176                 compatible = "qca,ar7200-usb-phy";
 177
 178                 reset-names = "usb-phy", "usb-suspend-override";
 179                 resets = <&rst 4>, <&rst 3>;
 180
 181                 #phy-cells = <0>;
 182
 183                 status = "disabled";
 184         };
 185 };
 186
 187 &eth0 {
 188         compatible = "qca,ar9130-eth", "syscon";
 189         reg = <0x19000000 0x200
 190                 0x18070000 0x4>;
 191         pll-data = <0x1a000000 0x13000a44 0x00441099>;
 192         pll-reg = <0x4 0x14 20>;
 193         pll-handle = <&pll>;
 194         resets = <&rst 9>;
 195         reset-names = "mac";
 196         qca,mac-idx = <0>;
 197 };