ath79: add support for Ubiquiti ToughSwitch/EdgeSwitch 8XP
[oweals/openwrt.git] / target / linux / ath79 / dts / ar7242_ubnt_edgeswitch-8xp.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 #include "ar7242.dtsi"
8
9 / {
10         compatible = "ubnt,edgeswitch-8xp", "qca,ar7242";
11         model = "Ubiquiti EdgeSwitch 8XP";
12
13         chosen {
14                 bootargs = "console=ttyS0,115200n8";
15         };
16
17         aliases {
18                 led-boot = &led_usr;
19                 led-failsafe = &led_usr;
20                 led-running = &led_usr;
21                 led-upgrade = &led_usr;
22         };
23
24         leds {
25                 compatible = "gpio-leds";
26
27                 led_usr: usr {
28                         label = "ubnt:yellow:usr";
29                         gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
30                 };
31         };
32
33         keys {
34                 compatible = "gpio-keys";
35
36                 reset {
37                         linux,code = <KEY_RESTART>;
38                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
39                         debounce-interval = <60>;
40                 };
41         };
42
43         gpio_spi {
44                 compatible = "spi-gpio";
45                 #address-cells = <0x1>;
46                 ranges;
47
48                 sck-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
49                 mosi-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
50                 cs-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
51                 num-chipselects = <1>;
52
53                 gpio_hc595: gpio_spi@0 {
54                         compatible = "fairchild,74hc595";
55                         reg = <0>;
56                         registers-number = <2>;
57                         spi-max-frequency = <100000>;
58                         enable-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
59
60                         gpio-controller;
61                         #gpio-cells = <2>;
62                 };
63         };
64
65         gpio-export {
66                 compatible = "gpio-export";
67
68                 poe_24v_port1 {
69                         gpio-export,name = "ubnt:24v-poe:port1";
70                         gpio-export,output = <0>;
71                         gpios = <&gpio_hc595 1 GPIO_ACTIVE_HIGH>;
72                 };
73
74                 poe_48v_port1 {
75                         gpio-export,name = "ubnt:48v-poe:port1";
76                         gpio-export,output = <0>;
77                         gpios = <&gpio_hc595 0 GPIO_ACTIVE_HIGH>;
78                 };
79
80                 poe_24v_port2 {
81                         gpio-export,name = "ubnt:24v-poe:port2";
82                         gpio-export,output = <0>;
83                         gpios = <&gpio_hc595 3 GPIO_ACTIVE_HIGH>;
84                 };
85
86                 poe_48v_port2 {
87                         gpio-export,name = "ubnt:48v-poe:port2";
88                         gpio-export,output = <0>;
89                         gpios = <&gpio_hc595 2 GPIO_ACTIVE_HIGH>;
90                 };
91
92                 poe_24v_port3 {
93                         gpio-export,name = "ubnt:24v-poe:port3";
94                         gpio-export,output = <0>;
95                         gpios = <&gpio_hc595 5 GPIO_ACTIVE_HIGH>;
96                 };
97
98                 poe_48v_port3 {
99                         gpio-export,name = "ubnt:48v-poe:port3";
100                         gpio-export,output = <0>;
101                         gpios = <&gpio_hc595 4 GPIO_ACTIVE_HIGH>;
102                 };
103
104                 poe_24v_port4 {
105                         gpio-export,name = "ubnt:24v-poe:port4";
106                         gpio-export,output = <0>;
107                         gpios = <&gpio_hc595 7 GPIO_ACTIVE_HIGH>;
108                 };
109
110                 poe_48v_port4 {
111                         gpio-export,name = "ubnt:48v-poe:port4";
112                         gpio-export,output = <0>;
113                         gpios = <&gpio_hc595 6 GPIO_ACTIVE_HIGH>;
114                 };
115
116                 poe_24v_port5 {
117                         gpio-export,name = "ubnt:24v-poe:port5";
118                         gpio-export,output = <0>;
119                         gpios = <&gpio_hc595 9 GPIO_ACTIVE_HIGH>;
120                 };
121
122                 poe_48v_port5 {
123                         gpio-export,name = "ubnt:48v-poe:port5";
124                         gpio-export,output = <0>;
125                         gpios = <&gpio_hc595 8 GPIO_ACTIVE_HIGH>;
126                 };
127
128                 poe_24v_port6 {
129                         gpio-export,name = "ubnt:24v-poe:port6";
130                         gpio-export,output = <0>;
131                         gpios = <&gpio_hc595 11 GPIO_ACTIVE_HIGH>;
132                 };
133
134                 poe_48v_port6 {
135                         gpio-export,name = "ubnt:48v-poe:port6";
136                         gpio-export,output = <0>;
137                         gpios = <&gpio_hc595 10 GPIO_ACTIVE_HIGH>;
138                 };
139
140                 poe_24v_port7 {
141                         gpio-export,name = "ubnt:24v-poe:port7";
142                         gpio-export,output = <0>;
143                         gpios = <&gpio_hc595 13 GPIO_ACTIVE_HIGH>;
144                 };
145
146                 poe_48v_port7 {
147                         gpio-export,name = "ubnt:48v-poe:port7";
148                         gpio-export,output = <0>;
149                         gpios = <&gpio_hc595 12 GPIO_ACTIVE_HIGH>;
150                 };
151
152                 poe_24v_port8 {
153                         gpio-export,name = "ubnt:24v-poe:port8";
154                         gpio-export,output = <0>;
155                         gpios = <&gpio_hc595 15 GPIO_ACTIVE_HIGH>;
156                 };
157
158                 poe_48v_port8 {
159                         gpio-export,name = "ubnt:48v-poe:port8";
160                         gpio-export,output = <0>;
161                         gpios = <&gpio_hc595 14 GPIO_ACTIVE_HIGH>;
162                 };
163         };
164 };
165
166 &spi {
167         status = "okay";
168
169         num-cs = <1>;
170
171         flash@0 {
172                 compatible = "jedec,spi-nor";
173                 reg = <0>;
174                 spi-max-frequency = <25000000>;
175
176                 partitions {
177                         compatible = "fixed-partitions";
178                         #address-cells = <1>;
179                         #size-cells = <1>;
180
181                         partition@0 {
182                                 reg = <0x000000 0x040000>;
183                                 label = "u-boot";
184                                 read-only;
185                         };
186
187                         partition@40000 {
188                                 reg = <0x040000 0x010000>;
189                                 label = "u-boot-env";
190                                 read-only;
191                         };
192
193                         partition@50000 {
194                                 compatible = "denx,uimage";
195                                 reg = <0x050000 0x760000>;
196                                 label = "firmware";
197                         };
198
199                         partition@7b0000 {
200                                 reg = <0x7b0000 0x040000>;
201                                 label = "cfg";
202                                 read-only;
203                         };
204
205                         art: partition@7f0000 {
206                                 reg = <0x7f0000 0x010000>;
207                                 label = "art";
208                                 read-only;
209                         };
210                 };
211         };
212 };
213
214 &mdio0 {
215         status = "okay";
216
217         phy-mask = <0x10>;
218
219         ethernet-switch@1e {
220                 compatible = "brcm,bcm53128";
221                 #address-cells = <1>;
222                 #size-cells = <0>;
223                 reg = <0x1e>;
224
225                 ports {
226                         port0@0 {
227                                 reg = <0>;
228                                 label = "lan1";
229                         };
230
231                         port1@1 {
232                                 reg = <1>;
233                                 label = "lan2";
234                         };
235
236                         port2@2 {
237                                 reg = <2>;
238                                 label = "lan3";
239                         };
240
241                         port3@3 {
242                                 reg = <3>;
243                                 label = "lan4";
244                         };
245
246                         port4@4 {
247                                 reg = <4>;
248                                 label = "lan5";
249                         };
250
251                         port5@5 {
252                                 reg = <5>;
253                                 label = "lan6";
254                         };
255
256                         port6@6 {
257                                 reg = <6>;
258                                 label = "lan7";
259                         };
260
261                         port7@7 {
262                                 reg = <7>;
263                                 label = "lan8";
264                         };
265
266                         phy0: port8@8 {
267                                 reg = <8>;
268                                 label = "cpu";
269                                 ethernet = <&eth0>;
270
271                                 fixed-link {
272                                         speed = <1000>;
273                                         full-duplex;
274                                 };
275                         };
276
277                 };
278         };
279 };
280
281 &usb_phy {
282         status = "okay";
283 };
284
285 &usb {
286         #address-cells = <1>;
287         #size-cells = <0>;
288         status = "okay";
289
290         hub_port: port@1 {
291                 reg = <1>;
292                 #trigger-source-cells = <0>;
293         };
294 };
295
296 &pcie {
297         status = "okay";
298 };
299
300 &uart {
301         status = "okay";
302 };
303
304 &eth0 {
305         status = "okay";
306
307         phy-mode = "rgmii-rxid";
308         pll-data = <0x16000000 0x00000101 0x00001313>;
309         mtd-mac-address = <&art 0x0>;
310
311         phy-handle = <&phy0>;
312         fixed-link {
313                 speed = <1000>;
314                 full-duplex;
315         };
316 };
317
318 &eth1 {
319         status = "okay";
320
321         mtd-mac-address = <&art 0x6>;
322 };