1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
6 compatible = "qca,ar7100";
14 compatible = "mips,mips24Kc";
15 clocks = <&pll ATH79_CLK_CPU>;
22 ddr_ctrl: memory-controller@18000000 {
23 compatible = "qca,ar7100-ddr-controller";
24 reg = <0x18000000 0x100>;
26 #qca,ddr-wb-channel-cells = <1>;
30 compatible = "ns16550a";
31 reg = <0x18020000 0x20>;
34 clocks = <&pll ATH79_CLK_AHB>;
44 usb_phy: usb-phy@18030000 {
45 compatible = "qca,ar7100-usb-phy";
46 reg = <0x18030000 0x10>;
48 reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
49 resets = <&rst 4>, <&rst 5>, <&rst 6>;
57 compatible = "qca,ar7100-gpio";
58 reg = <0x18040000 0x30>;
67 #interrupt-cells = <2>;
70 pll: pll-controller@18050000 {
71 compatible = "qca,ar7100-pll", "syscon";
72 reg = <0x18050000 0x20>;
75 /* The board must provides the ref clock */
78 clock-output-names = "cpu", "ddr", "ahb";
82 compatible = "qca,ar7130-wdt";
83 reg = <0x18060008 0x8>;
87 clocks = <&pll ATH79_CLK_AHB>;
92 rst: reset-controller@18060024 {
93 compatible = "qca,ar7100-reset";
94 reg = <0x18060024 0x4>;
99 pcie0: pcie-controller@180c0000 {
100 compatible = "qca,ar7100-pci";
101 #address-cells = <3>;
103 bus-range = <0x0 0x0>;
104 reg = <0x17010000 0x100>;
105 reg-names = "cfg_base";
106 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
107 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
108 interrupt-parent = <&cpuintc>;
111 interrupt-controller;
112 #interrupt-cells = <1>;
114 interrupt-map-mask = <0 0 0 1>;
115 interrupt-map = <0 0 0 0 &pcie0 0>;
122 compatible = "generic-ehci";
123 reg = <0x1b000000 0x1000>;
125 interrupt-parent = <&cpuintc>;
128 phy-names = "usb-phy";
137 compatible = "generic-ohci";
138 reg = <0x1c000000 0x1000>;
140 interrupt-parent = <&miscintc>;
143 phy-names = "usb-phy";
150 compatible = "qca,ar7100-spi";
151 reg = <0x1f000000 0x10>;
153 clocks = <&pll ATH79_CLK_AHB>;
156 #address-cells = <1>;
164 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
165 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
166 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
170 compatible = "qca,ar7100-misc-intc";
174 compatible = "qca,ar7100-eth";
175 reg = <0x19000000 0x200
178 pll-data = <0x00110000 0x00001099 0x00991099>;
179 pll-reg = <0x4 0x10 17>;
183 resets = <&rst 8>, <&rst 9>;
184 reset-names = "phy", "mac";
192 compatible = "qca,ar7100-eth";
193 reg = <0x1a000000 0x200
196 pll-data = <0x00110000 0x00001099 0x00991099>;
197 pll-reg = <0x4 0x14 19>;
202 resets = <&rst 12>, <&rst 13>;
203 reset-names = "phy", "mac";