target/linux/ath79/dts/ar7100.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 #include <dt-bindings/clock/ath79-clk.h>
   3 #include "ath79.dtsi"
   4
   5 / {
   6         compatible = "qca,ar7100";
   7
   8         cpus {
   9                 #address-cells = <1>;
  10                 #size-cells = <0>;
  11
  12                 cpu@0 {
  13                         device_type = "cpu";
  14                         compatible = "mips,mips24Kc";
  15                         clocks = <&pll ATH79_CLK_CPU>;
  16                         reg = <0>;
  17                 };
  18         };
  19
  20         ahb {
  21                 apb {
  22                         ddr_ctrl: memory-controller@18000000 {
  23                                 compatible = "qca,ar7100-ddr-controller";
  24                                 reg = <0x18000000 0x100>;
  25
  26                                 #qca,ddr-wb-channel-cells = <1>;
  27                         };
  28
  29                         uart: uart@18020000 {
  30                                 compatible = "ns16550a";
  31                                 reg = <0x18020000 0x20>;
  32                                 interrupts = <3>;
  33
  34                                 clocks = <&pll ATH79_CLK_AHB>;
  35                                 clock-names = "uart";
  36
  37                                 reg-io-width = <4>;
  38                                 reg-shift = <2>;
  39                                 no-loopback-test;
  40
  41                                 status = "disabled";
  42                         };
  43
  44                         usb_phy: usb-phy@18030000 {
  45                                 compatible = "qca,ar7100-usb-phy";
  46                                 reg = <0x18030000 0x10>;
  47
  48                                 reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
  49                                 resets = <&rst 4>, <&rst 5>, <&rst 6>;
  50
  51                                 #phy-cells = <0>;
  52
  53                                 status = "disabled";
  54                         };
  55
  56                         gpio: gpio@18040000 {
  57                                 compatible = "qca,ar7100-gpio";
  58                                 reg = <0x18040000 0x30>;
  59                                 interrupts = <2>;
  60
  61                                 ngpios = <16>;
  62
  63                                 gpio-controller;
  64                                 #gpio-cells = <2>;
  65
  66                                 interrupt-controller;
  67                                 #interrupt-cells = <2>;
  68                         };
  69
  70                         pll: pll-controller@18050000 {
  71                                 compatible = "qca,ar7100-pll", "syscon";
  72                                 reg = <0x18050000 0x20>;
  73
  74                                 clock-names = "ref";
  75                                 /* The board must provides the ref clock */
  76
  77                                 #clock-cells = <1>;
  78                                 clock-output-names = "cpu", "ddr", "ahb";
  79                         };
  80
  81                         wdt: wdt@18060008 {
  82                                 compatible = "qca,ar7130-wdt";
  83                                 reg = <0x18060008 0x8>;
  84
  85                                 interrupts = <4>;
  86
  87                                 clocks = <&pll ATH79_CLK_AHB>;
  88                                 clock-names = "wdt";
  89                         };
  90
  91
  92                         rst: reset-controller@18060024 {
  93                                 compatible = "qca,ar7100-reset";
  94                                 reg = <0x18060024 0x4>;
  95
  96                                 #reset-cells = <1>;
  97                         };
  98
  99                         pcie0: pcie-controller@180c0000 {
 100                                 compatible = "qca,ar7100-pci";
 101                                 #address-cells = <3>;
 102                                 #size-cells = <2>;
 103                                 bus-range = <0x0 0x0>;
 104                                 reg = <0x17010000 0x100>;
 105                                 reg-names = "cfg_base";
 106                                 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000        /* pci memory */
 107                                           0x1000000 0 0x00000000 0x0000000 0 0x000001>;         /* io space */
 108                                 interrupt-parent = <&cpuintc>;
 109                                 interrupts = <2>;
 110
 111                                 interrupt-controller;
 112                                 #interrupt-cells = <1>;
 113
 114                                 interrupt-map-mask = <0 0 0 1>;
 115                                 interrupt-map = <0 0 0 0 &pcie0 0>;
 116                                 status = "disabled";
 117                         };
 118                 };
 119         };
 120
 121         usb2: usb@1b000000 {
 122                 compatible = "generic-ehci";
 123                 reg = <0x1b000000 0x1000>;
 124
 125                 interrupt-parent = <&cpuintc>;
 126                 interrupts = <3>;
 127
 128                 phy-names = "usb-phy";
 129                 phys = <&usb_phy>;
 130
 131                 has-synopsys-hc-bug;
 132
 133                 status = "disabled";
 134         };
 135
 136         usb1: usb@1c000000 {
 137                 compatible = "generic-ohci";
 138                 reg = <0x1c000000 0x1000>;
 139
 140                 interrupt-parent = <&miscintc>;
 141                 interrupts = <6>;
 142
 143                 phy-names = "usb-phy";
 144                 phys = <&usb_phy>;
 145
 146                 status = "disabled";
 147         };
 148
 149         spi: spi@1f000000 {
 150                 compatible = "qca,ar7100-spi";
 151                 reg = <0x1f000000 0x10>;
 152
 153                 clocks = <&pll ATH79_CLK_AHB>;
 154                 clock-names = "ahb";
 155
 156                 #address-cells = <1>;
 157                 #size-cells = <0>;
 158
 159                 status = "disabled";
 160         };
 161 };
 162
 163 &cpuintc {
 164         qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
 165         qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
 166                                 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
 167 };
 168
 169 &miscintc {
 170         compatible = "qca,ar7100-misc-intc";
 171 };
 172
 173 &eth0 {
 174         compatible = "qca,ar7100-eth";
 175         reg = <0x19000000 0x200
 176                 0x18070000 0x4>;
 177
 178         pll-data = <0x00110000 0x00001099 0x00991099>;
 179         pll-reg = <0x4 0x10 17>;
 180         pll-handle = <&pll>;
 181         phy-mode = "rgmii";
 182
 183         resets = <&rst 8>, <&rst 9>;
 184         reset-names = "phy", "mac";
 185 };
 186
 187 &mdio1 {
 188         builtin-switch;
 189 };
 190
 191 &eth1 {
 192         compatible = "qca,ar7100-eth";
 193         reg = <0x1a000000 0x200
 194                 0x18070004 0x4>;
 195
 196         pll-data = <0x00110000 0x00001099 0x00991099>;
 197         pll-reg = <0x4 0x14 19>;
 198         pll-handle = <&pll>;
 199
 200         phy-mode = "rgmii";
 201
 202         resets = <&rst 12>, <&rst 13>;
 203         reset-names = "phy", "mac";
 204 };