2 * Support for peripherals on the AXS10x mainboard
4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 compatible = "simple-bus";
16 ranges = <0x00000000 0xe0000000 0x10000000>;
17 interrupt-parent = <&mb_intc>;
21 compatible = "fixed-clock";
22 clock-frequency = <50000000>;
27 compatible = "fixed-clock";
28 clock-frequency = <50000000>;
33 compatible = "fixed-clock";
34 clock-frequency = <50000000>;
40 #interrupt-cells = <1>;
41 compatible = "snps,dwmac";
42 reg = < 0x18000 0x2000 >;
44 interrupt-names = "macirq";
48 clock-names = "stmmaceth";
52 compatible = "generic-ehci";
53 reg = < 0x40000 0x100 >;
58 compatible = "generic-ohci";
59 reg = < 0x60000 0x100 >;
64 * According to DW Mobile Storage databook it is required
65 * to use "Hold Register" if card is enumerated in SDR12 or
68 * Utilization of "Hold Register" is already implemented via
69 * dw_mci_pltfm_prepare_command() which in its turn gets
70 * used through dw_mci_drv_data->prepare_command call-back.
71 * This call-back is used in Altera Socfpga platform and so
72 * we may reuse it saying that we're compatible with their
73 * "altr,socfpga-dw-mshc".
75 * Most probably "Hold Register" utilization is platform-
76 * independent requirement which means that single unified
77 * "snps,dw-mshc" should be enough for all users of DW MMC once
78 * dw_mci_pltfm_prepare_command() is used in generic platform
82 compatible = "altr,socfpga-dw-mshc";
83 reg = < 0x15000 0x400 >;
86 card-detect-delay = < 200 >;
87 clocks = <&apbclk>, <&mmcclk>;
88 clock-names = "biu", "ciu";
94 compatible = "snps,dw-apb-uart";
95 reg = <0x20000 0x100>;
96 clock-frequency = <33333333>;
104 compatible = "snps,dw-apb-uart";
105 reg = <0x21000 0x100>;
106 clock-frequency = <33333333>;
113 /* UART muxed with USB data port (ttyS3) */
115 compatible = "snps,dw-apb-uart";
116 reg = <0x22000 0x100>;
117 clock-frequency = <33333333>;
125 compatible = "snps,designware-i2c";
126 reg = <0x1d000 0x100>;
127 clock-frequency = <400000>;
133 compatible = "snps,designware-i2c";
134 reg = <0x1e000 0x100>;
135 clock-frequency = <400000>;
141 compatible = "snps,designware-i2c";
142 #address-cells = <1>;
144 reg = <0x1f000 0x100>;
145 clock-frequency = <400000>;
150 compatible = "24c01";
156 compatible = "24c04";
163 compatible = "snps,dw-apb-gpio";
164 reg = <0x13000 0x1000>;
165 #address-cells = <1>;
168 gpio0_banka: gpio-controller@0 {
169 compatible = "snps,dw-apb-gpio-port";
172 snps,nr-gpios = <32>;
176 gpio0_bankb: gpio-controller@1 {
177 compatible = "snps,dw-apb-gpio-port";
184 gpio0_bankc: gpio-controller@2 {
185 compatible = "snps,dw-apb-gpio-port";
194 compatible = "snps,dw-apb-gpio";
195 reg = <0x14000 0x1000>;
196 #address-cells = <1>;
199 gpio1_banka: gpio-controller@0 {
200 compatible = "snps,dw-apb-gpio-port";
203 snps,nr-gpios = <30>;
207 gpio1_bankb: gpio-controller@1 {
208 compatible = "snps,dw-apb-gpio-port";
211 snps,nr-gpios = <10>;
215 gpio1_bankc: gpio-controller@2 {
216 compatible = "snps,dw-apb-gpio-port";