target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -134,7 +134,7 @@
   4  #define QCA955X_PCI_CTRL_SIZE  0x100
   5
   6  #define QCA955X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
   7 -#define QCA955X_GMAC_SIZE      0x40
   8 +#define QCA955X_GMAC_SIZE      0x64
   9  #define QCA955X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
  10  #define QCA955X_WMAC_SIZE      0x20000
  11  #define QCA955X_EHCI0_BASE     0x1b000000
  12 @@ -1269,7 +1269,11 @@
  13   */
  14
  15  #define QCA955X_GMAC_REG_ETH_CFG       0x00
  16 +#define QCA955X_GMAC_REG_SGMII_RESET   0x14
  17  #define QCA955X_GMAC_REG_SGMII_SERDES  0x18
  18 +#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
  19 +#define QCA955X_GMAC_REG_MR_AN_STATUS  0x20
  20 +#define QCA955X_GMAC_REG_SGMII_DEBUG   0x58
  21
  22  #define QCA955X_ETH_CFG_RGMII_EN       BIT(0)
  23  #define QCA955X_ETH_CFG_MII_GE0                BIT(1)
  24 @@ -1291,6 +1295,18 @@
  25  #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
  26  #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT        20
  27
  28 +#define QCA955X_SGMII_RESET_RX_CLK_N_RESET     0x0
  29 +#define QCA955X_SGMII_RESET_RX_CLK_N           BIT(0)
  30 +#define QCA955X_SGMII_RESET_TX_CLK_N           BIT(1)
  31 +#define QCA955X_SGMII_RESET_RX_125M_N          BIT(2)
  32 +#define QCA955X_SGMII_RESET_TX_125M_N          BIT(3)
  33 +#define QCA955X_SGMII_RESET_HW_RX_125M_N       BIT(4)
  34 +
  35 +#define QCA955X_MR_AN_CONTROL_PHY_RESET        BIT(15)
  36 +#define QCA955X_MR_AN_CONTROL_AN_ENABLE        BIT(12)
  37 +
  38 +#define QCA955X_MR_AN_STATUS_AN_ABILITY        BIT(3)
  39 +
  40  #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS        BIT(15)
  41  #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
  42  #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf