target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -649,6 +649,7 @@
   4
   5  #define AR933X_BOOTSTRAP_MDIO_GPIO_EN  BIT(18)
   6  #define AR933X_BOOTSTRAP_EEPBUSY       BIT(4)
   7 +#define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3)
   8  #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
   9
  10  #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)
  11 @@ -678,6 +679,8 @@
  12
  13  #define QCA956X_BOOTSTRAP_REF_CLK_40   BIT(2)
  14
  15 +#define AR933X_USB_CONFIG_HOST_ONLY   BIT(8)
  16 +
  17  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
  18  #define AR934X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
  19  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)
  20 --- a/arch/mips/ath79/dev-usb.c
  21 +++ b/arch/mips/ath79/dev-usb.c
  22 @@ -19,6 +19,9 @@
  23  #include <linux/platform_device.h>
  24  #include <linux/usb/ehci_pdriver.h>
  25  #include <linux/usb/ohci_pdriver.h>
  26 +#include <linux/usb/otg.h>
  27 +#include <linux/usb/chipidea.h>
  28 +#include <linux/usb/usb_phy_generic.h>
  29
  30  #include <asm/mach-ath79/ath79.h>
  31  #include <asm/mach-ath79/ar71xx_regs.h>
  32 @@ -170,6 +173,54 @@ static void __init ar913x_usb_setup(void
  33                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  34  }
  35
  36 +static void __init ar933x_usb_setup_ctrl_config(void)
  37 +{
  38 +       void __iomem *usb_ctrl_base, *usb_config_reg;
  39 +       u32 usb_config;
  40 +
  41 +       usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
  42 +       usb_config_reg = usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG;
  43 +       usb_config = __raw_readl(usb_config_reg);
  44 +       usb_config &= ~AR933X_USB_CONFIG_HOST_ONLY;
  45 +       __raw_writel(usb_config, usb_config_reg);
  46 +       iounmap(usb_ctrl_base);
  47 +}
  48 +
  49 +static void __init ar933x_ci_usb_setup(void)
  50 +{
  51 +       u32 bootstrap;
  52 +       enum usb_dr_mode dr_mode;
  53 +       struct ci_hdrc_platform_data ci_pdata;
  54 +       struct platform_device *phy;
  55 +
  56 +       bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  57 +       if (bootstrap & AR933X_BOOTSTRAP_USB_MODE_HOST) {
  58 +               dr_mode = USB_DR_MODE_HOST;
  59 +       } else {
  60 +               dr_mode = USB_DR_MODE_PERIPHERAL;
  61 +               ar933x_usb_setup_ctrl_config();
  62 +       }
  63 +
  64 +       memset(&ci_pdata, 0, sizeof(ci_pdata));
  65 +       ci_pdata.name = "ci_hdrc_ar933x";
  66 +       ci_pdata.capoffset = DEF_CAPOFFSET;
  67 +       ci_pdata.dr_mode = dr_mode;
  68 +       ci_pdata.flags = CI_HDRC_DUAL_ROLE_NOT_OTG | CI_HDRC_DP_ALWAYS_PULLUP;
  69 +       ci_pdata.vbus_extcon.edev = ERR_PTR(-ENODEV);
  70 +       ci_pdata.id_extcon.edev = ERR_PTR(-ENODEV);
  71 +       ci_pdata.itc_setting = 1;
  72 +
  73 +       /* register a nop PHY */
  74 +       phy = usb_phy_generic_register();
  75 +       if (IS_ERR(phy))
  76 +               return;
  77 +
  78 +       ath79_usb_register("ci_hdrc", -1,
  79 +                          AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
  80 +                          ATH79_CPU_IRQ(3),
  81 +                          &ci_pdata, sizeof(ci_pdata));
  82 +}
  83 +
  84  static void __init ar933x_usb_setup(void)
  85  {
  86         ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
  87 @@ -185,6 +236,8 @@ static void __init ar933x_usb_setup(void
  88                            AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
  89                            ATH79_CPU_IRQ(3),
  90                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  91 +
  92 +       ar933x_ci_usb_setup();
  93  }
  94
  95  static void enable_tx_tx_idp_violation_fix(unsigned base)