1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Sat, 14 May 2016 20:20:04 +0200
3 Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer
6 AR913x, AR724x and AR933x are the only SoCs where the
7 ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
8 Invert the logic to make the code compatible with AR95xx
10 Signed-off-by: Felix Fietkau <nbd@nbd.name>
13 --- a/arch/mips/ath79/common.c
14 +++ b/arch/mips/ath79/common.c
15 @@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void)
17 ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
18 AR71XX_DDR_CTRL_SIZE);
19 - if (soc_is_ar71xx() || soc_is_ar934x()) {
20 - ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
21 - ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
23 + if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
24 ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
25 ath79_ddr_pci_win_base = 0;
27 + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
28 + ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
31 EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);