target/linux/ar71xx/patches-4.14/953-qca955x-pci-reset-fixes.patch

   1 --- a/arch/mips/ath79/common.c
   2 +++ b/arch/mips/ath79/common.c
   3 @@ -153,6 +153,24 @@ void ath79_device_reset_clear(u32 mask)
   4  }
   5  EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
   6
   7 +void ath79_device_reset2_clear(u32 mask)
   8 +{
   9 +       unsigned long flags;
  10 +       u32 reg;
  11 +       u32 t;
  12 +
  13 +       if (soc_is_qca955x())
  14 +               reg = QCA955X_RESET_REG_RESET2_MODULE;
  15 +       else
  16 +               panic("Reset register not defined for this SOC");
  17 +
  18 +       spin_lock_irqsave(&ath79_device_reset_lock, flags);
  19 +       t = ath79_reset_rr(reg);
  20 +       ath79_reset_wr(reg, t & ~mask);
  21 +       spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
  22 +}
  23 +EXPORT_SYMBOL_GPL(ath79_device_reset2_clear);
  24 +
  25  u32 ath79_device_reset_get(u32 mask)
  26  {
  27         unsigned long flags;
  28 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  29 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  30 @@ -411,6 +411,7 @@
  31  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
  32  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
  33  #define QCA955X_PLL_CLK_CTRL_REG               0x08
  34 +#define QCA955X_PLL_PCIE_CONFIG_REG            0x0c
  35  #define QCA955X_PLL_ETH_XMII_CONTROL_REG       0x28
  36  #define QCA955X_PLL_ETH_SGMII_CONTROL_REG      0x48
  37  #define QCA955X_PLL_ETH_SGMII_SERDES_REG       0x4c
  38 @@ -565,6 +566,7 @@
  39  #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  40
  41  #define QCA955X_RESET_REG_RESET_MODULE         0x1c
  42 +#define QCA955X_RESET_REG_RESET2_MODULE                0xc4
  43  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
  44  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
  45
  46 --- a/arch/mips/include/asm/mach-ath79/ath79.h
  47 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
  48 @@ -178,6 +178,7 @@ static inline u32 ath79_reset_rr(unsigne
  49
  50  void ath79_device_reset_set(u32 mask);
  51  void ath79_device_reset_clear(u32 mask);
  52 +void ath79_device_reset2_clear(u32 mask);
  53  u32 ath79_device_reset_get(u32 mask);
  54
  55  void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
  56 --- a/arch/mips/pci/pci-ar724x.c
  57 +++ b/arch/mips/pci/pci-ar724x.c
  58 @@ -335,18 +335,37 @@ static void ar724x_pci_hw_init(struct ar
  59         int wait = 0;
  60
  61         /* deassert PCIe host controller and PCIe PHY reset */
  62 -       ath79_device_reset_clear(AR724X_RESET_PCIE);
  63 -       ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
  64 +       if (soc_is_qca955x()) {
  65 +               ath79_device_reset_clear(QCA955X_RESET_PCIE);
  66 +               mdelay(10);
  67 +               ath79_device_reset_clear(QCA955X_RESET_PCIE_PHY);
  68 +               mdelay(10);
  69 +               ath79_device_reset2_clear(QCA955X_RESET_PCIE);
  70 +               mdelay(10);
  71 +               ath79_device_reset2_clear(QCA955X_RESET_PCIE_PHY);
  72 +               mdelay(10);
  73 +       } else {
  74 +               ath79_device_reset_clear(AR724X_RESET_PCIE);
  75 +               ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
  76 +       }
  77
  78         /* remove the reset of the PCIE PLL */
  79 -       ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  80 -       ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
  81 -       ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  82 +       if (!soc_is_qca955x()) {
  83 +               ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  84 +               ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
  85 +               ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  86 +       }
  87
  88         /* deassert bypass for the PCIE PLL */
  89 -       ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  90 -       ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
  91 -       ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  92 +       if (soc_is_qca955x()) {
  93 +               ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
  94 +               ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
  95 +               ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
  96 +       } else {
  97 +               ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  98 +               ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
  99 +               ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
 100 +       }
 101
 102         /* set PCIE Application Control to ready */
 103         app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
 104 @@ -422,8 +441,14 @@ static int ar724x_pci_probe(struct platf
 105          * Do the full PCIE Root Complex Initialization Sequence if the PCIe
 106          * host controller is in reset.
 107          */
 108 -       if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
 109 -               ar724x_pci_hw_init(apc);
 110 +       if (soc_is_qca955x()) {
 111 +               if (ath79_reset_rr(QCA955X_RESET_REG_RESET_MODULE) & QCA955X_RESET_PCIE ||
 112 +                   ath79_reset_rr(QCA955X_RESET_REG_RESET2_MODULE) & QCA955X_RESET_PCIE)
 113 +                       ar724x_pci_hw_init(apc);
 114 +       } else {
 115 +               if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
 116 +                       ar724x_pci_hw_init(apc);
 117 +       }
 118
 119         apc->link_up = ar724x_pci_check_link(apc);
 120         if (!apc->link_up)