target/linux/ar71xx/patches-4.14/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -157,6 +157,10 @@
   4  #define QCA956X_EHCI0_BASE     0x1b000000
   5  #define QCA956X_EHCI1_BASE     0x1b400000
   6  #define QCA956X_EHCI_SIZE      0x200
   7 +#define QCA956X_GMAC_SGMII_BASE        (AR71XX_APB_BASE + 0x00070000)
   8 +#define QCA956X_GMAC_SGMII_SIZE        0x64
   9 +#define QCA956X_PLL_BASE       (AR71XX_APB_BASE + 0x00050000)
  10 +#define QCA956X_PLL_SIZE       0x50
  11  #define QCA956X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
  12  #define QCA956X_GMAC_SIZE      0x64
  13
  14 @@ -414,6 +418,7 @@
  15  #define QCA956X_PLL_DDR_CONFIG_REG                     0x08
  16  #define QCA956X_PLL_DDR_CONFIG1_REG                    0x0c
  17  #define QCA956X_PLL_CLK_CTRL_REG                       0x10
  18 +#define QCA956X_PLL_ETH_XMII_CONTROL_REG               0x30
  19
  20  #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT            12
  21  #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK             0x1f
  22 @@ -1196,4 +1201,16 @@
  23  #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
  24  #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT        20
  25
  26 +/*
  27 + * QCA956X GMAC Interface
  28 + */
  29 +
  30 +#define QCA956X_GMAC_REG_ETH_CFG               0x00
  31 +
  32 +#define QCA956X_ETH_CFG_SW_ONLY_MODE           BIT(7)
  33 +#define QCA956X_ETH_CFG_SW_PHY_SWAP                BIT(8)
  34 +#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP       BIT(9)
  35 +#define QCA956X_ETH_CFG_SW_APB_ACCESS          BIT(10)
  36 +#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
  37 +
  38  #endif /* __ASM_MACH_AR71XX_REGS_H */