1 --- a/drivers/net/phy/at803x.c
2 +++ b/drivers/net/phy/at803x.c
7 +#include <linux/mdio.h>
8 #include <linux/module.h>
9 #include <linux/string.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/of_gpio.h>
13 #include <linux/gpio/consumer.h>
14 +#include <linux/platform_data/phy-at803x.h>
16 #define AT803X_INTR_ENABLE 0x12
17 #define AT803X_INTR_STATUS 0x13
19 #define AT803X_INER 0x0012
20 #define AT803X_INER_INIT 0xec00
21 #define AT803X_INSR 0x0013
23 +#define AT803X_PCS_SMART_EEE_CTRL3 0x805D
24 +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_MASK 0x3
25 +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT 12
26 +#define AT803X_SMART_EEE_CTRL3_LPI_EN BIT(8)
28 #define AT803X_DEBUG_ADDR 0x1D
29 #define AT803X_DEBUG_DATA 0x1E
30 +#define AT803X_DBG0_REG 0x00
31 +#define AT803X_DEBUG_RGMII_RX_CLK_DLY BIT(8)
32 #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
33 #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
35 @@ -61,6 +71,43 @@ struct at803x_context {
40 +at803x_dbg_reg_rmw(struct phy_device *phydev, u16 reg, u16 clear, u16 set)
42 + struct mii_bus *bus = phydev->bus;
45 + mutex_lock(&bus->mdio_lock);
47 + bus->write(bus, phydev->addr, AT803X_DEBUG_ADDR, reg);
48 + val = bus->read(bus, phydev->addr, AT803X_DEBUG_DATA);
56 + bus->write(bus, phydev->addr, AT803X_DEBUG_DATA, val);
59 + mutex_unlock(&bus->mdio_lock);
64 +at803x_dbg_reg_set(struct phy_device *phydev, u16 reg, u16 set)
66 + at803x_dbg_reg_rmw(phydev, reg, 0, set);
70 +at803x_dbg_reg_clr(struct phy_device *phydev, u16 reg, u16 clear)
72 + at803x_dbg_reg_rmw(phydev, reg, clear, 0);
76 /* save relevant PHY registers to private copy */
77 static void at803x_context_save(struct phy_device *phydev,
78 struct at803x_context *context)
79 @@ -208,8 +255,16 @@ static int at803x_probe(struct phy_devic
83 +static void at803x_disable_smarteee(struct phy_device *phydev)
85 + phy_write_mmd(phydev, MDIO_MMD_PCS, AT803X_PCS_SMART_EEE_CTRL3,
86 + 1 << AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT);
87 + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
90 static int at803x_config_init(struct phy_device *phydev)
92 + struct at803x_platform_data *pdata;
95 ret = genphy_config_init(phydev);
96 @@ -227,6 +282,26 @@ static int at803x_config_init(struct phy
100 + pdata = dev_get_platdata(&phydev->dev);
102 + if (pdata->disable_smarteee)
103 + at803x_disable_smarteee(phydev);
105 + if (pdata->enable_rgmii_rx_delay)
106 + at803x_dbg_reg_set(phydev, AT803X_DBG0_REG,
107 + AT803X_DEBUG_RGMII_RX_CLK_DLY);
109 + at803x_dbg_reg_clr(phydev, AT803X_DBG0_REG,
110 + AT803X_DEBUG_RGMII_RX_CLK_DLY);
112 + if (pdata->enable_rgmii_tx_delay)
113 + at803x_dbg_reg_set(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL,
114 + AT803X_DEBUG_RGMII_TX_CLK_DLY);
116 + at803x_dbg_reg_clr(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL,
117 + AT803X_DEBUG_RGMII_TX_CLK_DLY);
124 +++ b/include/linux/platform_data/phy-at803x.h
126 +#ifndef _PHY_AT803X_PDATA_H
127 +#define _PHY_AT803X_PDATA_H
129 +struct at803x_platform_data {
130 + int disable_smarteee:1;
131 + int enable_rgmii_tx_delay:1;
132 + int enable_rgmii_rx_delay:1;
135 +#endif /* _PHY_AT803X_PDATA_H */