2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
34 static struct resource ath79_mdio0_resources[] = {
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
51 .platform_data = &ath79_mdio0_data,
55 static struct resource ath79_mdio1_resources[] = {
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
72 .platform_data = &ath79_mdio1_data,
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
83 t = __raw_readl(base + cfg_reg);
86 __raw_writel(t, base + cfg_reg);
89 __raw_writel(pll_val, base + pll_reg);
92 __raw_writel(t, base + cfg_reg);
96 __raw_writel(t, base + cfg_reg);
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
124 unsigned int mii_speed;
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
166 clk = clk_get(NULL, "ref");
168 ret = clk_get_rate(clk);
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558 ||
187 ath79_soc == ATH79_SOC_QCA956X)
193 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
198 case ATH79_SOC_AR7241:
199 case ATH79_SOC_AR9330:
200 case ATH79_SOC_AR9331:
201 case ATH79_SOC_QCA9533:
202 case ATH79_SOC_TP9343:
203 mdio_dev = &ath79_mdio1_device;
204 mdio_data = &ath79_mdio1_data;
207 case ATH79_SOC_AR9341:
208 case ATH79_SOC_AR9342:
209 case ATH79_SOC_AR9344:
210 case ATH79_SOC_QCA9556:
211 case ATH79_SOC_QCA9558:
212 case ATH79_SOC_QCA956X:
214 mdio_dev = &ath79_mdio0_device;
215 mdio_data = &ath79_mdio0_data;
217 mdio_dev = &ath79_mdio1_device;
218 mdio_data = &ath79_mdio1_data;
222 case ATH79_SOC_AR7242:
223 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
224 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
225 AR71XX_ETH0_PLL_SHIFT);
228 mdio_dev = &ath79_mdio0_device;
229 mdio_data = &ath79_mdio0_data;
233 mdio_data->phy_mask = phy_mask;
236 case ATH79_SOC_AR7240:
237 mdio_data->is_ar7240 = 1;
239 case ATH79_SOC_AR7241:
240 mdio_data->builtin_switch = 1;
243 case ATH79_SOC_AR9330:
244 mdio_data->is_ar9330 = 1;
246 case ATH79_SOC_AR9331:
247 mdio_data->builtin_switch = 1;
250 case ATH79_SOC_AR9341:
251 case ATH79_SOC_AR9342:
252 case ATH79_SOC_AR9344:
254 mdio_data->builtin_switch = 1;
255 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
256 mdio_data->mdio_clock = 6250000;
258 mdio_data->is_ar934x = 1;
261 case ATH79_SOC_QCA9533:
262 case ATH79_SOC_TP9343:
263 mdio_data->builtin_switch = 1;
266 case ATH79_SOC_QCA9556:
267 case ATH79_SOC_QCA9558:
268 mdio_data->is_ar934x = 1;
271 case ATH79_SOC_QCA956X:
273 mdio_data->builtin_switch = 1;
274 mdio_data->is_ar934x = 1;
281 platform_device_register(mdio_dev);
284 struct ath79_eth_pll_data ath79_eth0_pll_data;
285 struct ath79_eth_pll_data ath79_eth1_pll_data;
287 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
289 struct ath79_eth_pll_data *pll_data;
294 pll_data = &ath79_eth0_pll_data;
297 pll_data = &ath79_eth1_pll_data;
305 pll_val = pll_data->pll_10;
308 pll_val = pll_data->pll_100;
311 pll_val = pll_data->pll_1000;
320 static void ath79_set_speed_ge0(int speed)
322 u32 val = ath79_get_eth_pll(0, speed);
324 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
325 val, AR71XX_ETH0_PLL_SHIFT);
326 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
329 static void ath79_set_speed_ge1(int speed)
331 u32 val = ath79_get_eth_pll(1, speed);
333 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
334 val, AR71XX_ETH1_PLL_SHIFT);
335 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
338 static void ar7242_set_speed_ge0(int speed)
340 u32 val = ath79_get_eth_pll(0, speed);
343 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
344 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
348 static void ar91xx_set_speed_ge0(int speed)
350 u32 val = ath79_get_eth_pll(0, speed);
352 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
353 val, AR913X_ETH0_PLL_SHIFT);
354 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
357 static void ar91xx_set_speed_ge1(int speed)
359 u32 val = ath79_get_eth_pll(1, speed);
361 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
362 val, AR913X_ETH1_PLL_SHIFT);
363 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
366 static void ar934x_set_speed_ge0(int speed)
369 u32 val = ath79_get_eth_pll(0, speed);
371 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
372 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
376 static void qca955x_set_speed_xmii(int speed)
379 u32 val = ath79_get_eth_pll(0, speed);
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
386 static void qca955x_set_speed_sgmii(int speed)
389 u32 val = ath79_get_eth_pll(1, speed);
391 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
392 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
396 static void qca956x_set_speed_sgmii(int speed)
399 u32 val = ath79_get_eth_pll(0, speed);
401 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
402 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
406 static void ath79_set_speed_dummy(int speed)
410 static void ath79_ddr_no_flush(void)
414 static void ath79_ddr_flush_ge0(void)
416 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
419 static void ath79_ddr_flush_ge1(void)
421 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
424 static void ar724x_ddr_flush_ge0(void)
426 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
429 static void ar724x_ddr_flush_ge1(void)
431 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
434 static void ar91xx_ddr_flush_ge0(void)
436 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
439 static void ar91xx_ddr_flush_ge1(void)
441 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
444 static void ar933x_ddr_flush_ge0(void)
446 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
449 static void ar933x_ddr_flush_ge1(void)
451 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
454 static struct resource ath79_eth0_resources[] = {
457 .flags = IORESOURCE_MEM,
458 .start = AR71XX_GE0_BASE,
459 .end = AR71XX_GE0_BASE + 0x200 - 1,
462 .flags = IORESOURCE_IRQ,
463 .start = ATH79_CPU_IRQ(4),
464 .end = ATH79_CPU_IRQ(4),
468 struct ag71xx_platform_data ath79_eth0_data = {
469 .reset_bit = AR71XX_RESET_GE0_MAC,
472 struct platform_device ath79_eth0_device = {
475 .resource = ath79_eth0_resources,
476 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
478 .platform_data = &ath79_eth0_data,
482 static struct resource ath79_eth1_resources[] = {
485 .flags = IORESOURCE_MEM,
486 .start = AR71XX_GE1_BASE,
487 .end = AR71XX_GE1_BASE + 0x200 - 1,
490 .flags = IORESOURCE_IRQ,
491 .start = ATH79_CPU_IRQ(5),
492 .end = ATH79_CPU_IRQ(5),
496 struct ag71xx_platform_data ath79_eth1_data = {
497 .reset_bit = AR71XX_RESET_GE1_MAC,
500 struct platform_device ath79_eth1_device = {
503 .resource = ath79_eth1_resources,
504 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
506 .platform_data = &ath79_eth1_data,
510 struct ag71xx_switch_platform_data ath79_switch_data;
512 #define AR71XX_PLL_VAL_1000 0x00110000
513 #define AR71XX_PLL_VAL_100 0x00001099
514 #define AR71XX_PLL_VAL_10 0x00991099
516 #define AR724X_PLL_VAL_1000 0x00110000
517 #define AR724X_PLL_VAL_100 0x00001099
518 #define AR724X_PLL_VAL_10 0x00991099
520 #define AR7242_PLL_VAL_1000 0x16000000
521 #define AR7242_PLL_VAL_100 0x00000101
522 #define AR7242_PLL_VAL_10 0x00001616
524 #define AR913X_PLL_VAL_1000 0x1a000000
525 #define AR913X_PLL_VAL_100 0x13000a44
526 #define AR913X_PLL_VAL_10 0x00441099
528 #define AR933X_PLL_VAL_1000 0x00110000
529 #define AR933X_PLL_VAL_100 0x00001099
530 #define AR933X_PLL_VAL_10 0x00991099
532 #define AR934X_PLL_VAL_1000 0x16000000
533 #define AR934X_PLL_VAL_100 0x00000101
534 #define AR934X_PLL_VAL_10 0x00001616
536 #define QCA956X_PLL_VAL_1000 0x03000000
537 #define QCA956X_PLL_VAL_100 0x00000101
538 #define QCA956X_PLL_VAL_10 0x00001919
540 static void __init ath79_init_eth_pll_data(unsigned int id)
542 struct ath79_eth_pll_data *pll_data;
543 u32 pll_10, pll_100, pll_1000;
547 pll_data = &ath79_eth0_pll_data;
550 pll_data = &ath79_eth1_pll_data;
557 case ATH79_SOC_AR7130:
558 case ATH79_SOC_AR7141:
559 case ATH79_SOC_AR7161:
560 pll_10 = AR71XX_PLL_VAL_10;
561 pll_100 = AR71XX_PLL_VAL_100;
562 pll_1000 = AR71XX_PLL_VAL_1000;
565 case ATH79_SOC_AR7240:
566 case ATH79_SOC_AR7241:
567 pll_10 = AR724X_PLL_VAL_10;
568 pll_100 = AR724X_PLL_VAL_100;
569 pll_1000 = AR724X_PLL_VAL_1000;
572 case ATH79_SOC_AR7242:
573 pll_10 = AR7242_PLL_VAL_10;
574 pll_100 = AR7242_PLL_VAL_100;
575 pll_1000 = AR7242_PLL_VAL_1000;
578 case ATH79_SOC_AR9130:
579 case ATH79_SOC_AR9132:
580 pll_10 = AR913X_PLL_VAL_10;
581 pll_100 = AR913X_PLL_VAL_100;
582 pll_1000 = AR913X_PLL_VAL_1000;
585 case ATH79_SOC_AR9330:
586 case ATH79_SOC_AR9331:
587 pll_10 = AR933X_PLL_VAL_10;
588 pll_100 = AR933X_PLL_VAL_100;
589 pll_1000 = AR933X_PLL_VAL_1000;
592 case ATH79_SOC_AR9341:
593 case ATH79_SOC_AR9342:
594 case ATH79_SOC_AR9344:
595 case ATH79_SOC_QCA9533:
596 case ATH79_SOC_QCA9556:
597 case ATH79_SOC_QCA9558:
598 case ATH79_SOC_TP9343:
599 pll_10 = AR934X_PLL_VAL_10;
600 pll_100 = AR934X_PLL_VAL_100;
601 pll_1000 = AR934X_PLL_VAL_1000;
604 case ATH79_SOC_QCA956X:
605 pll_10 = QCA956X_PLL_VAL_10;
606 pll_100 = QCA956X_PLL_VAL_100;
607 pll_1000 = QCA956X_PLL_VAL_1000;
614 if (!pll_data->pll_10)
615 pll_data->pll_10 = pll_10;
617 if (!pll_data->pll_100)
618 pll_data->pll_100 = pll_100;
620 if (!pll_data->pll_1000)
621 pll_data->pll_1000 = pll_1000;
624 static int __init ath79_setup_phy_if_mode(unsigned int id,
625 struct ag71xx_platform_data *pdata)
632 case ATH79_SOC_AR7130:
633 case ATH79_SOC_AR7141:
634 case ATH79_SOC_AR7161:
635 case ATH79_SOC_AR9130:
636 case ATH79_SOC_AR9132:
637 switch (pdata->phy_if_mode) {
638 case PHY_INTERFACE_MODE_MII:
639 mii_if = AR71XX_MII0_CTRL_IF_MII;
641 case PHY_INTERFACE_MODE_GMII:
642 mii_if = AR71XX_MII0_CTRL_IF_GMII;
644 case PHY_INTERFACE_MODE_RGMII:
645 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
647 case PHY_INTERFACE_MODE_RMII:
648 mii_if = AR71XX_MII0_CTRL_IF_RMII;
653 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
656 case ATH79_SOC_AR7240:
657 case ATH79_SOC_AR7241:
658 case ATH79_SOC_AR9330:
659 case ATH79_SOC_AR9331:
660 case ATH79_SOC_QCA9533:
661 case ATH79_SOC_TP9343:
662 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
665 case ATH79_SOC_AR7242:
668 case ATH79_SOC_AR9341:
669 case ATH79_SOC_AR9342:
670 case ATH79_SOC_AR9344:
671 switch (pdata->phy_if_mode) {
672 case PHY_INTERFACE_MODE_MII:
673 case PHY_INTERFACE_MODE_GMII:
674 case PHY_INTERFACE_MODE_RGMII:
675 case PHY_INTERFACE_MODE_RMII:
682 case ATH79_SOC_QCA9556:
683 case ATH79_SOC_QCA9558:
684 case ATH79_SOC_QCA956X:
685 switch (pdata->phy_if_mode) {
686 case PHY_INTERFACE_MODE_MII:
687 case PHY_INTERFACE_MODE_RGMII:
688 case PHY_INTERFACE_MODE_SGMII:
701 case ATH79_SOC_AR7130:
702 case ATH79_SOC_AR7141:
703 case ATH79_SOC_AR7161:
704 case ATH79_SOC_AR9130:
705 case ATH79_SOC_AR9132:
706 switch (pdata->phy_if_mode) {
707 case PHY_INTERFACE_MODE_RMII:
708 mii_if = AR71XX_MII1_CTRL_IF_RMII;
710 case PHY_INTERFACE_MODE_RGMII:
711 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
716 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
719 case ATH79_SOC_AR7240:
720 case ATH79_SOC_AR7241:
721 case ATH79_SOC_AR9330:
722 case ATH79_SOC_AR9331:
723 case ATH79_SOC_QCA956X:
724 case ATH79_SOC_TP9343:
725 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
728 case ATH79_SOC_AR7242:
731 case ATH79_SOC_AR9341:
732 case ATH79_SOC_AR9342:
733 case ATH79_SOC_AR9344:
734 case ATH79_SOC_QCA9533:
735 switch (pdata->phy_if_mode) {
736 case PHY_INTERFACE_MODE_MII:
737 case PHY_INTERFACE_MODE_GMII:
744 case ATH79_SOC_QCA9556:
745 case ATH79_SOC_QCA9558:
746 switch (pdata->phy_if_mode) {
747 case PHY_INTERFACE_MODE_MII:
748 case PHY_INTERFACE_MODE_RGMII:
749 case PHY_INTERFACE_MODE_SGMII:
765 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
770 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
772 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
773 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
775 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
777 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
778 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
783 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
788 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
790 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
792 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
793 AR934X_ETH_CFG_MII_GMAC0 |
794 AR934X_ETH_CFG_GMII_GMAC0 |
795 AR934X_ETH_CFG_SW_ONLY_MODE |
796 AR934X_ETH_CFG_SW_PHY_SWAP);
800 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
802 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
807 void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
813 rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
814 rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
816 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
818 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
820 t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
821 AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
823 t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
824 rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
826 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
828 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
833 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
838 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
840 t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
842 t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
846 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
851 static int ath79_eth_instance __initdata;
852 void __init ath79_register_eth(unsigned int id)
854 struct platform_device *pdev;
855 struct ag71xx_platform_data *pdata;
859 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
863 ath79_init_eth_pll_data(id);
866 pdev = &ath79_eth0_device;
868 pdev = &ath79_eth1_device;
870 pdata = pdev->dev.platform_data;
872 pdata->max_frame_len = 1540;
873 pdata->desc_pktlen_mask = 0xfff;
875 err = ath79_setup_phy_if_mode(id, pdata);
878 "ar71xx: invalid PHY interface mode for GE%u\n", id);
883 case ATH79_SOC_AR7130:
885 pdata->ddr_flush = ath79_ddr_flush_ge0;
886 pdata->set_speed = ath79_set_speed_ge0;
888 pdata->ddr_flush = ath79_ddr_flush_ge1;
889 pdata->set_speed = ath79_set_speed_ge1;
893 case ATH79_SOC_AR7141:
894 case ATH79_SOC_AR7161:
896 pdata->ddr_flush = ath79_ddr_flush_ge0;
897 pdata->set_speed = ath79_set_speed_ge0;
899 pdata->ddr_flush = ath79_ddr_flush_ge1;
900 pdata->set_speed = ath79_set_speed_ge1;
905 case ATH79_SOC_AR7242:
907 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
908 AR71XX_RESET_GE0_PHY;
909 pdata->ddr_flush = ar724x_ddr_flush_ge0;
910 pdata->set_speed = ar7242_set_speed_ge0;
912 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
913 AR71XX_RESET_GE1_PHY;
914 pdata->ddr_flush = ar724x_ddr_flush_ge1;
915 pdata->set_speed = ath79_set_speed_dummy;
918 pdata->is_ar724x = 1;
920 if (!pdata->fifo_cfg1)
921 pdata->fifo_cfg1 = 0x0010ffff;
922 if (!pdata->fifo_cfg2)
923 pdata->fifo_cfg2 = 0x015500aa;
924 if (!pdata->fifo_cfg3)
925 pdata->fifo_cfg3 = 0x01f00140;
928 case ATH79_SOC_AR7241:
930 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
932 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
934 case ATH79_SOC_AR7240:
936 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
937 pdata->ddr_flush = ar724x_ddr_flush_ge0;
938 pdata->set_speed = ath79_set_speed_dummy;
940 pdata->phy_mask = BIT(4);
942 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
943 pdata->ddr_flush = ar724x_ddr_flush_ge1;
944 pdata->set_speed = ath79_set_speed_dummy;
946 pdata->speed = SPEED_1000;
947 pdata->duplex = DUPLEX_FULL;
948 pdata->switch_data = &ath79_switch_data;
950 ath79_switch_data.phy_poll_mask |= BIT(4);
953 pdata->is_ar724x = 1;
954 if (ath79_soc == ATH79_SOC_AR7240)
955 pdata->is_ar7240 = 1;
957 if (!pdata->fifo_cfg1)
958 pdata->fifo_cfg1 = 0x0010ffff;
959 if (!pdata->fifo_cfg2)
960 pdata->fifo_cfg2 = 0x015500aa;
961 if (!pdata->fifo_cfg3)
962 pdata->fifo_cfg3 = 0x01f00140;
965 case ATH79_SOC_AR9130:
967 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
968 pdata->set_speed = ar91xx_set_speed_ge0;
970 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
971 pdata->set_speed = ar91xx_set_speed_ge1;
973 pdata->is_ar91xx = 1;
976 case ATH79_SOC_AR9132:
978 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
979 pdata->set_speed = ar91xx_set_speed_ge0;
981 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
982 pdata->set_speed = ar91xx_set_speed_ge1;
984 pdata->is_ar91xx = 1;
988 case ATH79_SOC_AR9330:
989 case ATH79_SOC_AR9331:
991 pdata->reset_bit = AR933X_RESET_GE0_MAC |
992 AR933X_RESET_GE0_MDIO;
993 pdata->ddr_flush = ar933x_ddr_flush_ge0;
994 pdata->set_speed = ath79_set_speed_dummy;
996 pdata->phy_mask = BIT(4);
998 pdata->reset_bit = AR933X_RESET_GE1_MAC |
999 AR933X_RESET_GE1_MDIO;
1000 pdata->ddr_flush = ar933x_ddr_flush_ge1;
1001 pdata->set_speed = ath79_set_speed_dummy;
1003 pdata->speed = SPEED_1000;
1004 pdata->has_gbit = 1;
1005 pdata->duplex = DUPLEX_FULL;
1006 pdata->switch_data = &ath79_switch_data;
1008 ath79_switch_data.phy_poll_mask |= BIT(4);
1011 pdata->is_ar724x = 1;
1013 if (!pdata->fifo_cfg1)
1014 pdata->fifo_cfg1 = 0x0010ffff;
1015 if (!pdata->fifo_cfg2)
1016 pdata->fifo_cfg2 = 0x015500aa;
1017 if (!pdata->fifo_cfg3)
1018 pdata->fifo_cfg3 = 0x01f00140;
1021 case ATH79_SOC_AR9341:
1022 case ATH79_SOC_AR9342:
1023 case ATH79_SOC_AR9344:
1024 case ATH79_SOC_QCA9533:
1026 pdata->reset_bit = AR934X_RESET_GE0_MAC |
1027 AR934X_RESET_GE0_MDIO;
1028 pdata->set_speed = ar934x_set_speed_ge0;
1030 pdata->reset_bit = AR934X_RESET_GE1_MAC |
1031 AR934X_RESET_GE1_MDIO;
1032 pdata->set_speed = ath79_set_speed_dummy;
1034 pdata->switch_data = &ath79_switch_data;
1036 /* reset the built-in switch */
1037 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1038 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1041 pdata->ddr_flush = ath79_ddr_no_flush;
1042 pdata->has_gbit = 1;
1043 pdata->is_ar724x = 1;
1045 pdata->max_frame_len = SZ_16K - 1;
1046 pdata->desc_pktlen_mask = SZ_16K - 1;
1048 if (!pdata->fifo_cfg1)
1049 pdata->fifo_cfg1 = 0x0010ffff;
1050 if (!pdata->fifo_cfg2)
1051 pdata->fifo_cfg2 = 0x015500aa;
1052 if (!pdata->fifo_cfg3)
1053 pdata->fifo_cfg3 = 0x01f00140;
1056 case ATH79_SOC_TP9343:
1058 pdata->reset_bit = AR933X_RESET_GE0_MAC |
1059 AR933X_RESET_GE0_MDIO;
1060 pdata->set_speed = ath79_set_speed_dummy;
1062 if (!pdata->phy_mask)
1063 pdata->phy_mask = BIT(4);
1065 pdata->reset_bit = AR933X_RESET_GE1_MAC |
1066 AR933X_RESET_GE1_MDIO;
1067 pdata->set_speed = ath79_set_speed_dummy;
1069 pdata->speed = SPEED_1000;
1070 pdata->duplex = DUPLEX_FULL;
1071 pdata->switch_data = &ath79_switch_data;
1073 ath79_switch_data.phy_poll_mask |= BIT(4);
1076 pdata->ddr_flush = ath79_ddr_no_flush;
1077 pdata->has_gbit = 1;
1078 pdata->is_ar724x = 1;
1080 if (!pdata->fifo_cfg1)
1081 pdata->fifo_cfg1 = 0x0010ffff;
1082 if (!pdata->fifo_cfg2)
1083 pdata->fifo_cfg2 = 0x015500aa;
1084 if (!pdata->fifo_cfg3)
1085 pdata->fifo_cfg3 = 0x01f00140;
1088 case ATH79_SOC_QCA9556:
1089 case ATH79_SOC_QCA9558:
1091 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1092 QCA955X_RESET_GE0_MDIO;
1093 pdata->set_speed = qca955x_set_speed_xmii;
1095 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1096 QCA955X_RESET_GE1_MDIO;
1097 pdata->set_speed = qca955x_set_speed_sgmii;
1100 pdata->ddr_flush = ath79_ddr_no_flush;
1101 pdata->has_gbit = 1;
1102 pdata->is_ar724x = 1;
1105 * Limit the maximum frame length to 4095 bytes.
1106 * Although the documentation says that the hardware
1107 * limit is 16383 bytes but that does not work in
1108 * practice. It seems that the hardware only updates
1109 * the lowest 12 bits of the packet length field
1110 * in the RX descriptor.
1112 pdata->max_frame_len = SZ_4K - 1;
1113 pdata->desc_pktlen_mask = SZ_16K - 1;
1115 if (!pdata->fifo_cfg1)
1116 pdata->fifo_cfg1 = 0x0010ffff;
1117 if (!pdata->fifo_cfg2)
1118 pdata->fifo_cfg2 = 0x015500aa;
1119 if (!pdata->fifo_cfg3)
1120 pdata->fifo_cfg3 = 0x01f00140;
1123 case ATH79_SOC_QCA956X:
1125 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1126 QCA955X_RESET_GE0_MDIO;
1128 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1129 pdata->set_speed = qca956x_set_speed_sgmii;
1131 pdata->set_speed = ath79_set_speed_ge0;
1133 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1134 QCA955X_RESET_GE1_MDIO;
1136 pdata->set_speed = ath79_set_speed_dummy;
1138 pdata->switch_data = &ath79_switch_data;
1140 pdata->speed = SPEED_1000;
1141 pdata->duplex = DUPLEX_FULL;
1143 /* reset the built-in switch */
1144 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1145 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1148 pdata->ddr_flush = ath79_ddr_no_flush;
1149 pdata->has_gbit = 1;
1150 pdata->is_ar724x = 1;
1152 if (!pdata->fifo_cfg1)
1153 pdata->fifo_cfg1 = 0x0010ffff;
1154 if (!pdata->fifo_cfg2)
1155 pdata->fifo_cfg2 = 0x015500aa;
1156 if (!pdata->fifo_cfg3)
1157 pdata->fifo_cfg3 = 0x01f00140;
1164 switch (pdata->phy_if_mode) {
1165 case PHY_INTERFACE_MODE_GMII:
1166 case PHY_INTERFACE_MODE_RGMII:
1167 case PHY_INTERFACE_MODE_SGMII:
1168 if (!pdata->has_gbit) {
1169 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1178 if (!is_valid_ether_addr(pdata->mac_addr)) {
1179 random_ether_addr(pdata->mac_addr);
1181 "ar71xx: using random MAC address for eth%d\n",
1182 ath79_eth_instance);
1185 if (pdata->mii_bus_dev == NULL) {
1186 switch (ath79_soc) {
1187 case ATH79_SOC_AR9341:
1188 case ATH79_SOC_AR9342:
1189 case ATH79_SOC_AR9344:
1191 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1193 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1196 case ATH79_SOC_AR7241:
1197 case ATH79_SOC_AR9330:
1198 case ATH79_SOC_AR9331:
1199 case ATH79_SOC_QCA9533:
1200 case ATH79_SOC_TP9343:
1201 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1204 case ATH79_SOC_QCA9556:
1205 case ATH79_SOC_QCA9558:
1206 /* don't assign any MDIO device by default */
1209 case ATH79_SOC_QCA956X:
1210 if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII)
1211 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1215 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1220 /* Reset the device */
1221 ath79_device_reset_set(pdata->reset_bit);
1224 ath79_device_reset_clear(pdata->reset_bit);
1227 platform_device_register(pdev);
1228 ath79_eth_instance++;
1231 void __init ath79_set_mac_base(unsigned char *mac)
1233 memcpy(ath79_mac_base, mac, ETH_ALEN);
1236 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1240 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1241 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1244 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1245 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1247 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1248 memset(mac, 0, ETH_ALEN);
1249 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1254 static void __init ath79_set_mac_base_ascii(char *str)
1258 ath79_parse_ascii_mac(str, mac);
1259 ath79_set_mac_base(mac);
1262 static int __init ath79_ethaddr_setup(char *str)
1264 ath79_set_mac_base_ascii(str);
1267 __setup("ethaddr=", ath79_ethaddr_setup);
1269 static int __init ath79_kmac_setup(char *str)
1271 ath79_set_mac_base_ascii(str);
1274 __setup("kmac=", ath79_kmac_setup);
1276 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1284 if (!src || !is_valid_ether_addr(src)) {
1285 memset(dst, '\0', ETH_ALEN);
1289 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1295 dst[3] = (t >> 16) & 0xff;
1296 dst[4] = (t >> 8) & 0xff;
1300 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1307 if (!src || !is_valid_ether_addr(src)) {
1308 memset(dst, '\0', ETH_ALEN);
1312 for (i = 0; i < ETH_ALEN; i++)