target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/bootmem.h>
  19
  20 #include <asm/bootinfo.h>
  21 #include <asm/time.h>           /* for mips_hpt_frequency */
  22 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  23 #include <asm/mips_machine.h>
  24
  25 #include <asm/mach-ar71xx/ar71xx.h>
  26
  27 #include "machtype.h"
  28 #include "devices.h"
  29
  30 #define AR71XX_SYS_TYPE_LEN     64
  31
  32 u32 ar71xx_cpu_freq;
  33 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  34
  35 u32 ar71xx_ahb_freq;
  36 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  37
  38 u32 ar71xx_ddr_freq;
  39 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  40
  41 u32 ar71xx_ref_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_ref_freq);
  43
  44 enum ar71xx_soc_type ar71xx_soc;
  45 EXPORT_SYMBOL_GPL(ar71xx_soc);
  46
  47 u32 ar71xx_soc_rev;
  48 EXPORT_SYMBOL_GPL(ar71xx_soc_rev);
  49
  50 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  51
  52 static void ar71xx_restart(char *command)
  53 {
  54         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  55         for (;;)
  56                 if (cpu_wait)
  57                         cpu_wait();
  58 }
  59
  60 static void ar71xx_halt(void)
  61 {
  62         while (1)
  63                 cpu_wait();
  64 }
  65
  66 static void __init ar71xx_detect_mem_size(void)
  67 {
  68         unsigned long size;
  69
  70         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  71              size <<= 1) {
  72                 if (!memcmp(ar71xx_detect_mem_size,
  73                             ar71xx_detect_mem_size + size, 1024))
  74                         break;
  75         }
  76
  77         add_memory_region(0, size, BOOT_MEM_RAM);
  78 }
  79
  80 static void __init ar71xx_detect_sys_type(void)
  81 {
  82         char *chip = "????";
  83         u32 id;
  84         u32 major;
  85         u32 minor;
  86         u32 rev = 0;
  87
  88         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  89         major = id & REV_ID_MAJOR_MASK;
  90
  91         switch (major) {
  92         case REV_ID_MAJOR_AR71XX:
  93                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  94                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  95                 rev &= AR71XX_REV_ID_REVISION_MASK;
  96                 switch (minor) {
  97                 case AR71XX_REV_ID_MINOR_AR7130:
  98                         ar71xx_soc = AR71XX_SOC_AR7130;
  99                         chip = "7130";
 100                         break;
 101
 102                 case AR71XX_REV_ID_MINOR_AR7141:
 103                         ar71xx_soc = AR71XX_SOC_AR7141;
 104                         chip = "7141";
 105                         break;
 106
 107                 case AR71XX_REV_ID_MINOR_AR7161:
 108                         ar71xx_soc = AR71XX_SOC_AR7161;
 109                         chip = "7161";
 110                         break;
 111                 }
 112                 break;
 113
 114         case REV_ID_MAJOR_AR7240:
 115                 ar71xx_soc = AR71XX_SOC_AR7240;
 116                 chip = "7240";
 117                 rev = id & AR724X_REV_ID_REVISION_MASK;
 118                 break;
 119
 120         case REV_ID_MAJOR_AR7241:
 121                 ar71xx_soc = AR71XX_SOC_AR7241;
 122                 chip = "7241";
 123                 rev = id & AR724X_REV_ID_REVISION_MASK;
 124                 break;
 125
 126         case REV_ID_MAJOR_AR7242:
 127                 ar71xx_soc = AR71XX_SOC_AR7242;
 128                 chip = "7242";
 129                 rev = id & AR724X_REV_ID_REVISION_MASK;
 130                 break;
 131
 132         case REV_ID_MAJOR_AR913X:
 133                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 134                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 135                 rev &= AR91XX_REV_ID_REVISION_MASK;
 136                 switch (minor) {
 137                 case AR91XX_REV_ID_MINOR_AR9130:
 138                         ar71xx_soc = AR71XX_SOC_AR9130;
 139                         chip = "9130";
 140                         break;
 141
 142                 case AR91XX_REV_ID_MINOR_AR9132:
 143                         ar71xx_soc = AR71XX_SOC_AR9132;
 144                         chip = "9132";
 145                         break;
 146                 }
 147                 break;
 148
 149         case REV_ID_MAJOR_AR9330:
 150                 ar71xx_soc = AR71XX_SOC_AR9330;
 151                 chip = "9330";
 152                 rev = id & AR933X_REV_ID_REVISION_MASK;
 153                 break;
 154
 155         case REV_ID_MAJOR_AR9331:
 156                 ar71xx_soc = AR71XX_SOC_AR9331;
 157                 chip = "9331";
 158                 rev = id & AR933X_REV_ID_REVISION_MASK;
 159                 break;
 160
 161         case REV_ID_MAJOR_AR9341:
 162                 ar71xx_soc = AR71XX_SOC_AR9341;
 163                 chip = "9341";
 164                 rev = id & AR934X_REV_ID_REVISION_MASK;
 165                 break;
 166
 167         case REV_ID_MAJOR_AR9342:
 168                 ar71xx_soc = AR71XX_SOC_AR9342;
 169                 chip = "9342";
 170                 rev = id & AR934X_REV_ID_REVISION_MASK;
 171                 break;
 172
 173         case REV_ID_MAJOR_AR9344:
 174                 ar71xx_soc = AR71XX_SOC_AR9344;
 175                 chip = "9344";
 176                 rev = id & AR934X_REV_ID_REVISION_MASK;
 177                 break;
 178
 179         default:
 180                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 181         }
 182
 183         ar71xx_soc_rev = rev;
 184
 185         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 186         pr_info("SoC: %s\n", ar71xx_sys_type);
 187 }
 188
 189 static void __init ar934x_detect_sys_frequency(void)
 190 {
 191         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 192         u32 cpu_pll, ddr_pll;
 193         u32 bootstrap;
 194
 195         bootstrap = ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
 196         if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
 197                 ar71xx_ref_freq = 40 * 1000 * 1000;
 198         else
 199                 ar71xx_ref_freq = 25 * 1000 * 1000;
 200
 201         pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
 202         out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
 203         ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
 204         nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll);
 205         frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
 206
 207         cpu_pll = nint * ar71xx_ref_freq / ref_div;
 208         cpu_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 6));
 209         cpu_pll /= (1 << out_div);
 210
 211         pll = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CONFIG);
 212         out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
 213         ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
 214         nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll);
 215         frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
 216
 217         ddr_pll = nint * ar71xx_ref_freq / ref_div;
 218         ddr_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 10));
 219         ddr_pll /= (1 << out_div);
 220
 221         clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
 222
 223         if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) {
 224                 ar71xx_cpu_freq = ar71xx_ref_freq;
 225         } else {
 226                 postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
 227
 228                 if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 229                         ar71xx_cpu_freq = cpu_pll / (postdiv + 1);
 230                 else
 231                         ar71xx_cpu_freq = ddr_pll / (postdiv + 1);
 232         }
 233
 234         if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) {
 235                 ar71xx_ddr_freq = ar71xx_ref_freq;
 236         } else {
 237                 postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
 238
 239                 if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 240                         ar71xx_ddr_freq = ddr_pll / (postdiv + 1);
 241                 else
 242                         ar71xx_ddr_freq = cpu_pll / (postdiv + 1);
 243         }
 244
 245         if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) {
 246                 ar71xx_ahb_freq = ar71xx_ref_freq;
 247         } else {
 248                 postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
 249
 250                 if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 251                         ar71xx_ahb_freq = ddr_pll / (postdiv + 1);
 252                 else
 253                         ar71xx_ahb_freq = cpu_pll / (postdiv + 1);
 254         }
 255 }
 256
 257 static void __init ar91xx_detect_sys_frequency(void)
 258 {
 259         u32 pll;
 260         u32 freq;
 261         u32 div;
 262
 263         ar71xx_ref_freq = 5 * 1000 * 1000;
 264
 265         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 266
 267         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 268         freq = div * ar71xx_ref_freq;
 269
 270         ar71xx_cpu_freq = freq;
 271
 272         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 273         ar71xx_ddr_freq = freq / div;
 274
 275         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 276         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 277 }
 278
 279 static void __init ar71xx_detect_sys_frequency(void)
 280 {
 281         u32 pll;
 282         u32 freq;
 283         u32 div;
 284
 285         ar71xx_ref_freq = 40 * 1000 * 1000;
 286
 287         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 288
 289         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 290         freq = div * ar71xx_ref_freq;
 291
 292         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 293         ar71xx_cpu_freq = freq / div;
 294
 295         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 296         ar71xx_ddr_freq = freq / div;
 297
 298         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 299         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 300 }
 301
 302 static void __init ar724x_detect_sys_frequency(void)
 303 {
 304         u32 pll;
 305         u32 freq;
 306         u32 div;
 307
 308         ar71xx_ref_freq = 5 * 1000 * 1000;
 309
 310         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 311
 312         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 313         freq = div * ar71xx_ref_freq;
 314
 315         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 316         freq *= div;
 317
 318         ar71xx_cpu_freq = freq;
 319
 320         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 321         ar71xx_ddr_freq = freq / div;
 322
 323         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 324         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 325 }
 326
 327 static void __init ar933x_detect_sys_frequency(void)
 328 {
 329         u32 clock_ctrl;
 330         u32 cpu_config;
 331         u32 freq;
 332         u32 t;
 333
 334         t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 335         if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 336                 ar71xx_ref_freq = (40 * 1000 * 1000);
 337         else
 338                 ar71xx_ref_freq = (25 * 1000 * 1000);
 339
 340         clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
 341         if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
 342                 ar71xx_cpu_freq = ar71xx_ref_freq;
 343                 ar71xx_ahb_freq = ar71xx_ref_freq;
 344                 ar71xx_ddr_freq = ar71xx_ref_freq;
 345         } else {
 346                 cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
 347
 348                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 349                     AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
 350                 freq = ar71xx_ref_freq / t;
 351
 352                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
 353                     AR933X_PLL_CPU_CONFIG_NINT_MASK;
 354                 freq *= t;
 355
 356                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 357                     AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
 358                 if (t == 0)
 359                         t = 1;
 360
 361                 freq >>= t;
 362
 363                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
 364                      AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
 365                 ar71xx_cpu_freq = freq / t;
 366
 367                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
 368                       AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
 369                 ar71xx_ddr_freq = freq / t;
 370
 371                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
 372                      AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
 373                 ar71xx_ahb_freq = freq / t;
 374         }
 375 }
 376
 377 static void __init detect_sys_frequency(void)
 378 {
 379         switch (ar71xx_soc) {
 380         case AR71XX_SOC_AR7130:
 381         case AR71XX_SOC_AR7141:
 382         case AR71XX_SOC_AR7161:
 383                 ar71xx_detect_sys_frequency();
 384                 break;
 385
 386         case AR71XX_SOC_AR7240:
 387         case AR71XX_SOC_AR7241:
 388         case AR71XX_SOC_AR7242:
 389                 ar724x_detect_sys_frequency();
 390                 break;
 391
 392         case AR71XX_SOC_AR9130:
 393         case AR71XX_SOC_AR9132:
 394                 ar91xx_detect_sys_frequency();
 395                 break;
 396
 397         case AR71XX_SOC_AR9330:
 398         case AR71XX_SOC_AR9331:
 399                 ar933x_detect_sys_frequency();
 400                 break;
 401
 402         case AR71XX_SOC_AR9341:
 403         case AR71XX_SOC_AR9342:
 404         case AR71XX_SOC_AR9344:
 405                 ar934x_detect_sys_frequency();
 406                 break;
 407         default:
 408                 BUG();
 409         }
 410 }
 411
 412 const char *get_system_type(void)
 413 {
 414         return ar71xx_sys_type;
 415 }
 416
 417 unsigned int __cpuinit get_c0_compare_irq(void)
 418 {
 419         return CP0_LEGACY_COMPARE_IRQ;
 420 }
 421
 422 void __init plat_mem_setup(void)
 423 {
 424         set_io_port_base(KSEG1);
 425
 426         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 427                                                 AR71XX_DDR_CTRL_SIZE);
 428
 429         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 430                                                 AR71XX_PLL_SIZE);
 431
 432         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 433                                                 AR71XX_RESET_SIZE);
 434
 435         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 436
 437         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 438                                                 AR71XX_USB_CTRL_SIZE);
 439
 440         ar71xx_detect_mem_size();
 441         ar71xx_detect_sys_type();
 442         detect_sys_frequency();
 443
 444         pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
 445                 "Ref:%u.%03uMHz",
 446                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 447                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000,
 448                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 449                 ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000);
 450
 451         _machine_restart = ar71xx_restart;
 452         _machine_halt = ar71xx_halt;
 453         pm_power_off = ar71xx_halt;
 454 }
 455
 456 void __init plat_time_init(void)
 457 {
 458         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 459 }
 460
 461 __setup("board=", mips_machtype_setup);
 462
 463 static int __init ar71xx_machine_setup(void)
 464 {
 465         ar71xx_gpio_init();
 466
 467         ar71xx_add_device_uart();
 468         ar71xx_add_device_wdt();
 469
 470         mips_machine_setup();
 471         return 0;
 472 }
 473
 474 arch_initcall(ar71xx_machine_setup);
 475
 476 static void __init ar71xx_generic_init(void)
 477 {
 478         /* Nothing to do */
 479 }
 480
 481 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
 482              ar71xx_generic_init);