2 * SPI controller driver for the Mikrotik RB4xx boards
4 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
6 * This file was based on the patches for Linux 2.6.27.39 published by
7 * MikroTik for their RouterBoard 4xx series devices.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/spinlock.h>
22 #include <linux/workqueue.h>
23 #include <linux/platform_device.h>
24 #include <linux/spi/spi.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/ath79.h>
29 #define DRV_NAME "rb4xx-spi"
30 #define DRV_DESC "Mikrotik RB4xx SPI controller driver"
31 #define DRV_VERSION "0.1.0"
33 #define SPI_CTRL_FASTEST 0x40
34 #define SPI_FLASH_HZ 33333334
35 #define SPI_CPLD_HZ 33333334
37 #define CPLD_CMD_READ_FAST 0x0b
39 #undef RB4XX_SPI_DEBUG
43 struct spi_master *master;
45 unsigned spi_ctrl_flash;
46 unsigned spi_ctrl_fread;
49 unsigned long ahb_freq;
52 struct list_head queue;
57 static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
59 #ifdef RB4XX_SPI_DEBUG
60 static inline void do_spi_delay(void)
65 static inline void do_spi_delay(void) { }
68 static inline void do_spi_init(struct spi_device *spi)
70 unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
72 if (!(spi->mode & SPI_CS_HIGH))
73 cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
79 static inline void do_spi_finish(void __iomem *base)
82 __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
83 base + AR71XX_SPI_REG_IOC);
86 static inline void do_spi_clk(void __iomem *base, int bit)
88 unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
91 __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
93 __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
96 static void do_spi_byte(void __iomem *base, unsigned char byte)
98 do_spi_clk(base, byte >> 7);
99 do_spi_clk(base, byte >> 6);
100 do_spi_clk(base, byte >> 5);
101 do_spi_clk(base, byte >> 4);
102 do_spi_clk(base, byte >> 3);
103 do_spi_clk(base, byte >> 2);
104 do_spi_clk(base, byte >> 1);
105 do_spi_clk(base, byte);
107 pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
109 (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
112 static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
115 unsigned bval = (spi_clk_low |
116 ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
117 ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
119 __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
121 __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
124 static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
126 do_spi_clk_fast(base, byte >> 7, byte >> 6);
127 do_spi_clk_fast(base, byte >> 5, byte >> 4);
128 do_spi_clk_fast(base, byte >> 3, byte >> 2);
129 do_spi_clk_fast(base, byte >> 1, byte >> 0);
131 pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
133 (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
136 static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
138 const unsigned char *rxv_ptr = NULL;
139 const unsigned char *tx_ptr = t->tx_buf;
140 unsigned char *rx_ptr = t->rx_buf;
143 pr_debug("spi_txrx len %u tx %u rx %u\n",
146 (t->rx_buf ? 1 : 0));
153 for (i = 0; i < t->len; ++i) {
154 unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
157 do_spi_byte_fast(base, sdata);
159 do_spi_byte(base, sdata);
162 rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
163 } else if (rxv_ptr) {
164 unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS);
173 static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi,
174 struct spi_message *m)
176 struct spi_transfer *t;
177 const unsigned char *tx_ptr;
179 void __iomem *base = rbspi->base;
181 /* check for exactly two transfers */
182 if (list_empty(&m->transfers) ||
183 list_is_last(m->transfers.next, &m->transfers) ||
184 !list_is_last(m->transfers.next->next, &m->transfers)) {
188 /* first transfer contains command and address */
189 t = list_entry(m->transfers.next,
190 struct spi_transfer, transfer_list);
192 if (t->len != 5 || t->tx_buf == NULL)
196 if (tx_ptr[0] != CPLD_CMD_READ_FAST)
200 addr = tx_ptr[2] | (addr << 8);
201 addr = tx_ptr[3] | (addr << 8);
202 addr += (unsigned) base;
204 m->actual_length += t->len;
206 /* second transfer contains data itself */
207 t = list_entry(m->transfers.next->next,
208 struct spi_transfer, transfer_list);
210 if (t->tx_buf && !t->verify)
213 __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
214 __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL);
215 __raw_writel(0, base + AR71XX_SPI_REG_FS);
218 memcpy(t->rx_buf, (const void *)addr, t->len);
219 } else if (t->tx_buf) {
220 unsigned char buf[t->len];
221 memcpy(buf, (const void *)addr, t->len);
222 if (memcmp(t->tx_buf, buf, t->len) != 0)
223 m->status = -EMSGSIZE;
225 m->actual_length += t->len;
227 if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
228 __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
229 __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
230 __raw_writel(0, base + AR71XX_SPI_REG_FS);
236 static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
238 struct spi_transfer *t = NULL;
239 void __iomem *base = rbspi->base;
242 if (list_empty(&m->transfers))
246 if (rb4xx_spi_read_fast(rbspi, m) == 0)
249 __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
250 __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
253 list_for_each_entry(t, &m->transfers, transfer_list) {
256 len = rb4xx_spi_txrx(base, t);
258 m->status = -EMSGSIZE;
261 m->actual_length += len;
264 if (list_is_last(&t->transfer_list, &m->transfers)) {
265 /* wait for continuation */
266 return m->spi->chip_select;
274 __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
275 __raw_writel(0, base + AR71XX_SPI_REG_FS);
279 static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
280 unsigned long *flags)
282 int cs = rbspi->cs_wait;
285 while (!list_empty(&rbspi->queue)) {
286 struct spi_message *m;
288 list_for_each_entry(m, &rbspi->queue, queue)
289 if (cs < 0 || cs == m->spi->chip_select)
292 if (&m->queue == &rbspi->queue)
295 list_del_init(&m->queue);
296 spin_unlock_irqrestore(&rbspi->lock, *flags);
298 cs = rb4xx_spi_msg(rbspi, m);
299 m->complete(m->context);
301 spin_lock_irqsave(&rbspi->lock, *flags);
308 /* TODO: add timer to unlock cs after 1s inactivity */
312 static int rb4xx_spi_transfer(struct spi_device *spi,
313 struct spi_message *m)
315 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
318 m->actual_length = 0;
319 m->status = -EINPROGRESS;
321 spin_lock_irqsave(&rbspi->lock, flags);
322 list_add_tail(&m->queue, &rbspi->queue);
324 (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
325 /* job will be done later */
326 spin_unlock_irqrestore(&rbspi->lock, flags);
330 /* process job in current context */
331 rb4xx_spi_process_queue_locked(rbspi, &flags);
332 spin_unlock_irqrestore(&rbspi->lock, flags);
337 static int rb4xx_spi_setup(struct spi_device *spi)
339 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
342 if (spi->mode & ~(SPI_CS_HIGH)) {
343 dev_err(&spi->dev, "mode %x not supported\n",
344 (unsigned) spi->mode);
348 if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
349 dev_err(&spi->dev, "bits_per_word %u not supported\n",
350 (unsigned) spi->bits_per_word);
354 spin_lock_irqsave(&rbspi->lock, flags);
355 if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
357 rb4xx_spi_process_queue_locked(rbspi, &flags);
359 spin_unlock_irqrestore(&rbspi->lock, flags);
364 static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
369 div = (rbspi->ahb_freq - 1) / (2 * hz_max);
372 * CPU has a bug at (div == 0) - first bit read is random
378 unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
379 unsigned div_real = 2 * (div + 1);
380 pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
386 return SPI_CTRL_FASTEST + div;
389 static int rb4xx_spi_probe(struct platform_device *pdev)
391 struct spi_master *master;
392 struct rb4xx_spi *rbspi;
396 master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
397 if (master == NULL) {
398 dev_err(&pdev->dev, "no memory for spi_master\n");
404 master->num_chipselect = 3;
405 master->setup = rb4xx_spi_setup;
406 master->transfer = rb4xx_spi_transfer;
408 rbspi = spi_master_get_devdata(master);
410 rbspi->ahb_clk = clk_get(&pdev->dev, "ahb");
411 if (IS_ERR(rbspi->ahb_clk)) {
412 err = PTR_ERR(rbspi->ahb_clk);
416 err = clk_enable(rbspi->ahb_clk);
420 rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
421 if (!rbspi->ahb_freq) {
423 goto err_clk_disable;
426 platform_set_drvdata(pdev, rbspi);
428 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
431 goto err_clk_disable;
434 rbspi->base = ioremap(r->start, r->end - r->start + 1);
437 goto err_clk_disable;
440 rbspi->master = master;
441 rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
442 rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
445 spin_lock_init(&rbspi->lock);
446 INIT_LIST_HEAD(&rbspi->queue);
448 err = spi_register_master(master);
450 dev_err(&pdev->dev, "failed to register SPI master\n");
457 iounmap(rbspi->base);
459 clk_disable(rbspi->ahb_clk);
461 clk_put(rbspi->ahb_clk);
463 platform_set_drvdata(pdev, NULL);
464 spi_master_put(master);
469 static int rb4xx_spi_remove(struct platform_device *pdev)
471 struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
473 iounmap(rbspi->base);
474 clk_disable(rbspi->ahb_clk);
475 clk_put(rbspi->ahb_clk);
476 platform_set_drvdata(pdev, NULL);
477 spi_master_put(rbspi->master);
482 static struct platform_driver rb4xx_spi_drv = {
483 .probe = rb4xx_spi_probe,
484 .remove = rb4xx_spi_remove,
487 .owner = THIS_MODULE,
491 static int __init rb4xx_spi_init(void)
493 return platform_driver_register(&rb4xx_spi_drv);
495 subsys_initcall(rb4xx_spi_init);
497 static void __exit rb4xx_spi_exit(void)
499 platform_driver_unregister(&rb4xx_spi_drv);
502 module_exit(rb4xx_spi_exit);
504 MODULE_DESCRIPTION(DRV_DESC);
505 MODULE_VERSION(DRV_VERSION);
506 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
507 MODULE_LICENSE("GPL v2");