2 * Platform driver for the Realtek RTL8366 ethernet switch
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/spinlock.h>
18 #include <linux/skbuff.h>
19 #include <linux/phy.h>
20 #include <linux/rtl8366_smi.h>
24 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
25 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
26 #define RTL8366_SMI_DRIVER_VER "0.1.0"
28 #define RTL8366S_PHY_NO_MAX 4
29 #define RTL8366S_PHY_PAGE_MAX 7
30 #define RTL8366S_PHY_ADDR_MAX 31
32 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
33 #define RTL8366S_CHIP_VERSION_MASK 0xf
34 #define RTL8366S_CHIP_ID_REG 0x0105
35 #define RTL8366S_CHIP_ID_8366 0x8366
37 /* PHY registers control */
38 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
39 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
41 #define RTL8366S_PHY_CTRL_READ 1
42 #define RTL8366S_PHY_CTRL_WRITE 0
44 #define RTL8366S_PHY_REG_MASK 0x1f
45 #define RTL8366S_PHY_PAGE_OFFSET 5
46 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
47 #define RTL8366S_PHY_NO_OFFSET 9
48 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
50 #define RTL8366_SMI_ACK_RETRY_COUNT 5
51 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
54 struct platform_device *pdev;
55 struct rtl8366_smi_platform_data *pdata;
57 struct mii_bus *mii_bus;
58 int mii_irq[PHY_MAX_ADDR];
61 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
63 ndelay(RTL8366_SMI_CLK_DELAY);
66 static void rtl8366_smi_start(struct rtl8366_smi *smi)
68 unsigned int sda = smi->pdata->gpio_sda;
69 unsigned int sck = smi->pdata->gpio_sck;
72 * Set GPIO pins to output mode, with initial state:
75 gpio_direction_output(sck, 0);
76 gpio_direction_output(sda, 1);
77 rtl8366_smi_clk_delay(smi);
79 /* CLK 1: 0 -> 1, 1 -> 0 */
80 gpio_set_value(sck, 1);
81 rtl8366_smi_clk_delay(smi);
82 gpio_set_value(sck, 0);
83 rtl8366_smi_clk_delay(smi);
86 gpio_set_value(sck, 1);
87 rtl8366_smi_clk_delay(smi);
88 gpio_set_value(sda, 0);
89 rtl8366_smi_clk_delay(smi);
90 gpio_set_value(sck, 0);
91 rtl8366_smi_clk_delay(smi);
92 gpio_set_value(sda, 1);
95 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
97 unsigned int sda = smi->pdata->gpio_sda;
98 unsigned int sck = smi->pdata->gpio_sck;
100 rtl8366_smi_clk_delay(smi);
101 gpio_set_value(sda, 0);
102 gpio_set_value(sck, 1);
103 rtl8366_smi_clk_delay(smi);
104 gpio_set_value(sda, 1);
105 rtl8366_smi_clk_delay(smi);
106 gpio_set_value(sck, 1);
107 rtl8366_smi_clk_delay(smi);
108 gpio_set_value(sck, 0);
109 rtl8366_smi_clk_delay(smi);
110 gpio_set_value(sck, 1);
113 rtl8366_smi_clk_delay(smi);
114 gpio_set_value(sck, 0);
115 rtl8366_smi_clk_delay(smi);
116 gpio_set_value(sck, 1);
118 /* set GPIO pins to input mode */
119 gpio_direction_input(sda);
120 gpio_direction_input(sck);
123 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
125 unsigned int sda = smi->pdata->gpio_sda;
126 unsigned int sck = smi->pdata->gpio_sck;
128 for (; len > 0; len--) {
129 rtl8366_smi_clk_delay(smi);
132 if ( data & ( 1 << (len - 1)) )
133 gpio_set_value(sda, 1);
135 gpio_set_value(sda, 0);
136 rtl8366_smi_clk_delay(smi);
139 gpio_set_value(sck, 1);
140 rtl8366_smi_clk_delay(smi);
141 gpio_set_value(sck, 0);
145 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
147 unsigned int sda = smi->pdata->gpio_sda;
148 unsigned int sck = smi->pdata->gpio_sck;
150 gpio_direction_input(sda);
152 for (*data = 0; len > 0; len--) {
155 rtl8366_smi_clk_delay(smi);
158 gpio_set_value(sck, 1);
159 rtl8366_smi_clk_delay(smi);
160 u = gpio_get_value(sda);
161 gpio_set_value(sck, 0);
163 *data |= (u << (len - 1));
166 gpio_direction_output(sda, 0);
169 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
177 rtl8366_smi_read_bits(smi, 1, &ack);
181 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
188 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
190 rtl8366_smi_write_bits(smi, data, 8);
191 return rtl8366_smi_wait_for_ack(smi);
194 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
199 rtl8366_smi_read_bits(smi, 8, &t);
203 rtl8366_smi_write_bits(smi, 0x00, 1);
208 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
213 rtl8366_smi_read_bits(smi, 8, &t);
217 rtl8366_smi_write_bits(smi, 0x01, 1);
222 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
229 spin_lock_irqsave(&smi->lock, flags);
231 rtl8366_smi_start(smi);
233 /* send READ command */
234 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
239 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
244 ret = rtl8366_smi_write_byte(smi, addr >> 8);
249 rtl8366_smi_read_byte0(smi, &lo);
250 /* read DATA[15:8] */
251 rtl8366_smi_read_byte1(smi, &hi);
253 *data = ((u32) lo) | (((u32) hi) << 8);
258 rtl8366_smi_stop(smi);
259 spin_unlock_irqrestore(&smi->lock, flags);
264 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
269 spin_lock_irqsave(&smi->lock, flags);
271 rtl8366_smi_start(smi);
273 /* send WRITE command */
274 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
279 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
284 ret = rtl8366_smi_write_byte(smi, addr >> 8);
288 /* write DATA[7:0] */
289 ret = rtl8366_smi_write_byte(smi, data & 0xff);
293 /* write DATA[15:8] */
294 ret = rtl8366_smi_write_byte(smi, data >> 8);
301 rtl8366_smi_stop(smi);
302 spin_unlock_irqrestore(&smi->lock, flags);
307 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
308 u32 phy_no, u32 page, u32 addr, u32 *data)
313 if (phy_no > RTL8366S_PHY_NO_MAX)
316 if (page > RTL8366S_PHY_PAGE_MAX)
319 if (addr > RTL8366S_PHY_ADDR_MAX)
322 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
323 RTL8366S_PHY_CTRL_READ);
327 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
328 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
329 (addr & RTL8366S_PHY_REG_MASK);
331 ret = rtl8366_smi_write_reg(smi, reg, 0);
335 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
342 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
343 u32 phy_no, u32 page, u32 addr, u32 data)
348 if (phy_no > RTL8366S_PHY_NO_MAX)
351 if (page > RTL8366S_PHY_PAGE_MAX)
354 if (addr > RTL8366S_PHY_ADDR_MAX)
357 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
358 RTL8366S_PHY_CTRL_WRITE);
362 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
363 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
364 (addr & RTL8366S_PHY_REG_MASK);
366 ret = rtl8366_smi_write_reg(smi, reg, data);
374 static void rtl8366_smi_dump_regs(struct rtl8366_smi *smi)
380 for (i = 0; i < 0x200; i++) {
381 err = rtl8366_smi_read_reg(smi, i, &t);
383 dev_err(&smi->pdev->dev,
384 "unable to read register %04x\n", i);
387 dev_info(&smi->pdev->dev, "reg %04x: %04x\n", i, t);
390 for (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) {
393 for (j = 0; j <= RTL8366S_PHY_ADDR_MAX; j++) {
394 err = rtl8366_smi_read_phy_reg(smi, i, 0, j, &t);
396 dev_err(&smi->pdev->dev,
397 "unable to read PHY%u:%02x register\n",
401 dev_info(&smi->pdev->dev,
402 "PHY%u:%02x: %04x\n", i, j, t);
407 static inline void rtl8366_smi_dump_regs(struct rtl8366_smi *smi) {}
410 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
412 struct rtl8366_smi *smi = bus->priv;
416 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
423 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
426 struct rtl8366_smi *smi = bus->priv;
430 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
432 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
437 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
442 smi->mii_bus = mdiobus_alloc();
443 if (smi->mii_bus == NULL) {
448 spin_lock_init(&smi->lock);
449 smi->mii_bus->priv = (void *) smi;
450 smi->mii_bus->name = "rtl8366-smi";
451 smi->mii_bus->read = rtl8366_smi_mii_read;
452 smi->mii_bus->write = rtl8366_smi_mii_write;
453 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
454 dev_name(&smi->pdev->dev));
455 smi->mii_bus->parent = &smi->pdev->dev;
456 smi->mii_bus->phy_mask = ~(0x1f);
457 smi->mii_bus->irq = smi->mii_irq;
458 for (i = 0; i < PHY_MAX_ADDR; i++)
459 smi->mii_irq[i] = PHY_POLL;
461 rtl8366_smi_dump_regs(smi);
463 ret = mdiobus_register(smi->mii_bus);
467 rtl8366_smi_dump_regs(smi);
472 mdiobus_free(smi->mii_bus);
477 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
479 mdiobus_unregister(smi->mii_bus);
480 mdiobus_free(smi->mii_bus);
483 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
489 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
491 dev_err(&smi->pdev->dev, "unable to read chip id\n");
496 case RTL8366S_CHIP_ID_8366:
499 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
503 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
506 dev_err(&smi->pdev->dev, "unable to read chip version\n");
510 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
511 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
516 static int __init rtl8366_smi_probe(struct platform_device *pdev)
518 static int rtl8366_smi_version_printed;
519 struct rtl8366_smi_platform_data *pdata;
520 struct rtl8366_smi *smi;
523 if (!rtl8366_smi_version_printed++)
524 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
525 " version " RTL8366_SMI_DRIVER_VER"\n");
527 pdata = pdev->dev.platform_data;
529 dev_err(&pdev->dev, "no platform data specified\n");
534 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
536 dev_err(&pdev->dev, "no memory for private data\n");
541 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
543 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
544 pdata->gpio_sda, err);
548 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
550 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
551 pdata->gpio_sck, err);
557 spin_lock_init(&smi->lock);
559 platform_set_drvdata(pdev, smi);
561 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
562 pdata->gpio_sda, pdata->gpio_sck);
564 err = rtl8366_smi_setup(smi);
566 goto err_clear_drvdata;
568 err = rtl8366_smi_mii_init(smi);
570 goto err_clear_drvdata;
575 platform_set_drvdata(pdev, NULL);
576 gpio_free(pdata->gpio_sck);
578 gpio_free(pdata->gpio_sda);
585 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
587 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
590 struct rtl8366_smi_platform_data *pdata;
592 pdata = pdev->dev.platform_data;
594 rtl8366_smi_mii_cleanup(smi);
595 platform_set_drvdata(pdev, NULL);
596 gpio_free(pdata->gpio_sck);
597 gpio_free(pdata->gpio_sda);
604 int rtl8366_phy_config_aneg(struct phy_device *phydev)
609 static struct platform_driver rtl8366_smi_driver = {
611 .name = RTL8366_SMI_DRIVER_NAME,
612 .owner = THIS_MODULE,
614 .probe = rtl8366_smi_probe,
615 .remove = __devexit_p(rtl8366_smi_remove),
618 static struct phy_driver rtl8366_smi_phy_driver = {
619 .phy_id = 0x001cc960,
620 .name = "Realtek RTL8366",
621 .phy_id_mask = 0x1ffffff0,
622 .features = PHY_GBIT_FEATURES,
623 .config_aneg = rtl8366_phy_config_aneg,
624 .read_status = genphy_read_status,
626 .owner = THIS_MODULE,
630 static int __init rtl8366_smi_init(void)
634 ret = phy_driver_register(&rtl8366_smi_phy_driver);
638 ret = platform_driver_register(&rtl8366_smi_driver);
640 goto err_phy_unregister;
645 phy_driver_unregister(&rtl8366_smi_phy_driver);
648 module_init(rtl8366_smi_init);
650 static void __exit rtl8366_smi_exit(void)
652 platform_driver_unregister(&rtl8366_smi_driver);
653 phy_driver_unregister(&rtl8366_smi_phy_driver);
655 module_exit(rtl8366_smi_exit);
657 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
658 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
659 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
660 MODULE_LICENSE("GPL v2");
661 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);