2 * Platform driver for the Realtek RTL8366 ethernet switch
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
27 #include <linux/debugfs.h>
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
132 RTL8366_PORT_UNKNOWN | \
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
139 RTL8366_PORT_UNKNOWN)
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
149 struct rtl8366s_vlanconfig {
160 struct rtl8366s_vlan4kentry {
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
172 "EtherStatsUnderSizePkts ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
213 struct dentry *debugfs_root;
221 #define to_rtl8366(_dev) container_of(_dev, struct rtl8366_smi, dev)
223 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
225 ndelay(RTL8366_SMI_CLK_DELAY);
228 static void rtl8366_smi_start(struct rtl8366_smi *smi)
230 unsigned int sda = smi->pdata->gpio_sda;
231 unsigned int sck = smi->pdata->gpio_sck;
234 * Set GPIO pins to output mode, with initial state:
237 gpio_direction_output(sck, 0);
238 gpio_direction_output(sda, 1);
239 rtl8366_smi_clk_delay(smi);
241 /* CLK 1: 0 -> 1, 1 -> 0 */
242 gpio_set_value(sck, 1);
243 rtl8366_smi_clk_delay(smi);
244 gpio_set_value(sck, 0);
245 rtl8366_smi_clk_delay(smi);
248 gpio_set_value(sck, 1);
249 rtl8366_smi_clk_delay(smi);
250 gpio_set_value(sda, 0);
251 rtl8366_smi_clk_delay(smi);
252 gpio_set_value(sck, 0);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sda, 1);
257 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
259 unsigned int sda = smi->pdata->gpio_sda;
260 unsigned int sck = smi->pdata->gpio_sck;
262 rtl8366_smi_clk_delay(smi);
263 gpio_set_value(sda, 0);
264 gpio_set_value(sck, 1);
265 rtl8366_smi_clk_delay(smi);
266 gpio_set_value(sda, 1);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sck, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sck, 0);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 1);
275 rtl8366_smi_clk_delay(smi);
276 gpio_set_value(sck, 0);
277 rtl8366_smi_clk_delay(smi);
278 gpio_set_value(sck, 1);
280 /* set GPIO pins to input mode */
281 gpio_direction_input(sda);
282 gpio_direction_input(sck);
285 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
287 unsigned int sda = smi->pdata->gpio_sda;
288 unsigned int sck = smi->pdata->gpio_sck;
290 for (; len > 0; len--) {
291 rtl8366_smi_clk_delay(smi);
294 if ( data & ( 1 << (len - 1)) )
295 gpio_set_value(sda, 1);
297 gpio_set_value(sda, 0);
298 rtl8366_smi_clk_delay(smi);
301 gpio_set_value(sck, 1);
302 rtl8366_smi_clk_delay(smi);
303 gpio_set_value(sck, 0);
307 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
309 unsigned int sda = smi->pdata->gpio_sda;
310 unsigned int sck = smi->pdata->gpio_sck;
312 gpio_direction_input(sda);
314 for (*data = 0; len > 0; len--) {
317 rtl8366_smi_clk_delay(smi);
320 gpio_set_value(sck, 1);
321 rtl8366_smi_clk_delay(smi);
322 u = gpio_get_value(sda);
323 gpio_set_value(sck, 0);
325 *data |= (u << (len - 1));
328 gpio_direction_output(sda, 0);
331 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
339 rtl8366_smi_read_bits(smi, 1, &ack);
343 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
350 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
352 rtl8366_smi_write_bits(smi, data, 8);
353 return rtl8366_smi_wait_for_ack(smi);
356 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
361 rtl8366_smi_read_bits(smi, 8, &t);
365 rtl8366_smi_write_bits(smi, 0x00, 1);
370 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
375 rtl8366_smi_read_bits(smi, 8, &t);
379 rtl8366_smi_write_bits(smi, 0x01, 1);
384 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
391 spin_lock_irqsave(&smi->lock, flags);
393 rtl8366_smi_start(smi);
395 /* send READ command */
396 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
401 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
406 ret = rtl8366_smi_write_byte(smi, addr >> 8);
411 rtl8366_smi_read_byte0(smi, &lo);
412 /* read DATA[15:8] */
413 rtl8366_smi_read_byte1(smi, &hi);
415 *data = ((u32) lo) | (((u32) hi) << 8);
420 rtl8366_smi_stop(smi);
421 spin_unlock_irqrestore(&smi->lock, flags);
426 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
431 spin_lock_irqsave(&smi->lock, flags);
433 rtl8366_smi_start(smi);
435 /* send WRITE command */
436 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
441 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
446 ret = rtl8366_smi_write_byte(smi, addr >> 8);
450 /* write DATA[7:0] */
451 ret = rtl8366_smi_write_byte(smi, data & 0xff);
455 /* write DATA[15:8] */
456 ret = rtl8366_smi_write_byte(smi, data >> 8);
463 rtl8366_smi_stop(smi);
464 spin_unlock_irqrestore(&smi->lock, flags);
469 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
470 u32 phy_no, u32 page, u32 addr, u32 *data)
475 if (phy_no > RTL8366S_PHY_NO_MAX)
478 if (page > RTL8366S_PHY_PAGE_MAX)
481 if (addr > RTL8366S_PHY_ADDR_MAX)
484 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
485 RTL8366S_PHY_CTRL_READ);
489 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
490 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
491 (addr & RTL8366S_PHY_REG_MASK);
493 ret = rtl8366_smi_write_reg(smi, reg, 0);
497 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
504 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
505 u32 phy_no, u32 page, u32 addr, u32 data)
510 if (phy_no > RTL8366S_PHY_NO_MAX)
513 if (page > RTL8366S_PHY_PAGE_MAX)
516 if (addr > RTL8366S_PHY_ADDR_MAX)
519 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
520 RTL8366S_PHY_CTRL_WRITE);
524 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
525 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
526 (addr & RTL8366S_PHY_REG_MASK);
528 ret = rtl8366_smi_write_reg(smi, reg, data);
535 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
536 int port, unsigned long long *val)
540 u32 addr, data, regoffset;
543 /* address offset to MIBs counter */
544 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
545 2, 2, 2, 2, 2, 2, 2, 2, 2,
546 2, 2, 4, 2, 2, 2, 2, 2, 2,
549 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
553 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
555 while (i < counter) {
556 regoffset += mibLength[i];
560 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
563 /* writing access counter address first */
564 /* then ASIC will prepare 64bits counter wait for being retrived */
565 data = 0;/* writing data will be discard by ASIC */
566 err = rtl8366_smi_write_reg(smi, addr, data);
570 /* read MIB control register */
571 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
575 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
578 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
582 addr = addr + mibLength[counter] - 1;
583 i = mibLength[counter];
586 err = rtl8366_smi_read_reg(smi, addr, &data);
590 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
600 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
601 struct rtl8366s_vlan4kentry *vlan4k)
607 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
610 if (vid >= RTL8366_NUM_VIDS)
613 tableaddr = (u16 *)vlan4k;
617 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
621 /* write table access control word */
622 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
623 RTL8366S_TABLE_VLAN_READ_CTRL);
627 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
634 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
645 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
646 const struct rtl8366s_vlan4kentry *vlan4k)
652 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
653 vlan4k->member > RTL8366_PORT_ALL ||
654 vlan4k->untag > RTL8366_PORT_ALL ||
655 vlan4k->fid > RTL8366S_FIDMAX)
658 tableaddr = (u16 *)vlan4k;
662 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
670 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
673 /* write table access control word */
674 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
675 RTL8366S_TABLE_VLAN_WRITE_CTRL);
682 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
683 struct rtl8366s_vlanconfig
691 memset(vlanmconf, '\0', sizeof(struct rtl8366s_vlanconfig));
693 if (index >= RTL8366_NUM_VLANS)
696 tableaddr = (u16 *)vlanmconf;
698 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
700 err = rtl8366_smi_read_reg(smi, addr, &data);
707 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
709 err = rtl8366_smi_read_reg(smi, addr, &data);
718 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
719 const struct rtl8366s_vlanconfig
727 if (index >= RTL8366_NUM_VLANS ||
728 vlanmconf->vid >= RTL8366_NUM_VIDS ||
729 vlanmconf->priority > RTL8366S_PRIORITYMAX ||
730 vlanmconf->member > RTL8366_PORT_ALL ||
731 vlanmconf->untag > RTL8366_PORT_ALL ||
732 vlanmconf->fid > RTL8366S_FIDMAX)
735 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
738 tableaddr = (u16 *)vlanmconf;
741 err = rtl8366_smi_write_reg(smi, addr, data);
745 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
750 err = rtl8366_smi_write_reg(smi, addr, data);
757 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
764 /* bits mapping to port vlan control register of port n */
765 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
766 0xF000, 0x000F, 0x00F0 };
767 /* bits offset to port vlan control register of port n */
768 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
769 /* address offset to port vlan control register of port n */
770 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
772 if (port >= RTL8366_NUM_PORTS)
775 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
777 err = rtl8366_smi_read_reg(smi, addr, &data);
781 *val = (data & bits[port]) >> bitoffset[port];
787 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
792 struct rtl8366s_vlanconfig vlanMC;
794 err = rtl8366_get_port_vlan_index(smi, port, &index);
798 err = rtl8366s_get_vlan_member_config(smi, index, &vlanMC);
806 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
815 /* bits mapping to port vlan control register of port n */
816 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
817 0xF000, 0x000F, 0x00F0 };
818 /* bits offset to port vlan control register of port n */
819 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
820 /* address offset to port vlan control register of port n */
821 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
823 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
826 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
828 bits = bitmasks[port];
830 data = (index << bitOff[port]) & bits;
832 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
836 vlan_data &= ~(vlan_data & bits);
839 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
846 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
850 struct rtl8366s_vlanconfig vlanMC;
851 struct rtl8366s_vlan4kentry vlan4K;
853 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
858 /* Updating the 4K entry; lookup it and change the port member set */
859 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4K);
860 vlan4K.member |= ((1 << port) | RTL8366_PORT_CPU);
861 vlan4K.untag = RTL8366_PORT_ALL_BUT_CPU;
862 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
864 /* For the 16 entries more work needs to be done. First see if such
865 VID is already there and change it */
866 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
867 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
869 /* Try to find an existing vid and update port member set */
870 if (val == vlanMC.vid) {
871 vlanMC.member |= ((1 << port) | RTL8366_PORT_CPU);
872 rtl8366s_set_vlan_member_config(smi, i, &vlanMC);
874 /* Now update PVID register settings */
875 rtl8366_set_port_vlan_index(smi, port, i);
881 /* PVID could not be found from vlan table. Replace unused (one that
882 has no member ports) with new one */
883 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
884 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
886 /* See if this vlan member configuration is unused. It is
887 unused if member set contains no ports or CPU port only */
888 if (!vlanMC.member || vlanMC.member == RTL8366_PORT_CPU) {
891 vlanMC.untag = RTL8366_PORT_ALL_BUT_CPU;
892 vlanMC.member = ((1 << port) | RTL8366_PORT_CPU);
895 rtl8366s_set_vlan_member_config(smi, i, &vlanMC);
897 /* Now update PVID register settings */
898 rtl8366_set_port_vlan_index(smi, port, i);
904 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
910 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
913 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
915 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
917 data |= RTL8366_CHIP_CTRL_VLAN;
919 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
922 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
925 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
931 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
934 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
937 struct rtl8366s_vlan4kentry vlan4K;
938 struct rtl8366s_vlanconfig vlanMC;
940 /* clear 16 VLAN member configuration */
941 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
947 if (rtl8366s_set_vlan_member_config(smi, i, &vlanMC) != 0)
951 /* Set a default VLAN with vid 1 to 4K table for all ports */
953 vlan4K.member = RTL8366_PORT_ALL;
954 vlan4K.untag = RTL8366_PORT_ALL;
956 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4K) != 0)
959 /* Set all ports PVID to default VLAN */
960 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
961 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
969 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
971 file->private_data = inode->i_private;
975 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
976 char __user *user_buf,
977 size_t count, loff_t *ppos)
981 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
983 len += snprintf(buf + len, sizeof(buf) - len, "MIB Counters:\n");
984 len += snprintf(buf + len, sizeof(buf) - len, "Counter"
986 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
989 for (i = 0; i < 33; ++i) {
991 len += snprintf(buf + len, sizeof(buf) - len, "%d:%s ",
993 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
994 unsigned long long counter = 0;
996 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
997 len += snprintf(buf + len, sizeof(buf) - len,
1000 len += snprintf(buf + len, sizeof(buf) - len,
1003 if (j != RTL8366_NUM_PORTS - 1) {
1004 if (counter < 100000)
1005 len += snprintf(buf + len,
1009 len += snprintf(buf + len, sizeof(buf) - len,
1013 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1016 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1018 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1021 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1022 char __user *user_buf,
1023 size_t count, loff_t *ppos)
1027 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1029 len += snprintf(buf + len, sizeof(buf) - len, "VLAN Member Config:\n");
1030 len += snprintf(buf + len, sizeof(buf) - len,
1031 "\t id \t vid \t prio \t member \t untag \t fid "
1034 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1035 struct rtl8366s_vlanconfig vlanMC;
1037 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
1039 len += snprintf(buf + len, sizeof(buf) - len,
1040 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1041 "\t", i, vlanMC.vid, vlanMC.priority,
1042 vlanMC.member, vlanMC.untag, vlanMC.fid);
1044 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1046 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1048 len += snprintf(buf + len,
1053 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1056 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1059 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1060 char __user *user_buf,
1061 size_t count, loff_t *ppos)
1063 u32 t, reg = g_dbg_reg;
1066 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1068 memset(buf, '\0', sizeof(buf));
1070 err = rtl8366_smi_read_reg(smi, reg, &t);
1072 len += snprintf(buf, sizeof(buf),
1073 "Read failed (reg: 0x%04x)\n", reg);
1074 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1077 len += snprintf(buf, sizeof(buf), "reg = 0x%04x, val = 0x%04x\n",
1080 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1083 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1084 const char __user *user_buf,
1085 size_t count, loff_t *ppos)
1088 u32 reg = g_dbg_reg;
1092 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1094 len = min(count, sizeof(buf) - 1);
1095 if (copy_from_user(buf, user_buf, len)) {
1096 dev_err(&smi->pdev->dev, "copy from user failed\n");
1101 if (len > 0 && buf[len - 1] == '\n')
1102 buf[len - 1] = '\0';
1105 if (strict_strtoul(buf, 16, &data)) {
1106 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1108 err = rtl8366_smi_write_reg(smi, reg, data);
1110 dev_err(&smi->pdev->dev,
1111 "writing reg 0x%04x val 0x%04lx failed\n",
1119 static const struct file_operations fops_rtl8366_regs = {
1120 .read = rtl8366_read_debugfs_reg,
1121 .write = rtl8366_write_debugfs_reg,
1122 .open = rtl8366_debugfs_open,
1123 .owner = THIS_MODULE
1126 static const struct file_operations fops_rtl8366_vlan = {
1127 .read = rtl8366_read_debugfs_vlan,
1128 .open = rtl8366_debugfs_open,
1129 .owner = THIS_MODULE
1132 static const struct file_operations fops_rtl8366_mibs = {
1133 .read = rtl8366_read_debugfs_mibs,
1134 .open = rtl8366_debugfs_open,
1135 .owner = THIS_MODULE
1138 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1140 struct dentry *node;
1141 struct dentry *root;
1143 if (!smi->debugfs_root)
1144 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1146 if (!smi->debugfs_root) {
1147 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1150 root = smi->debugfs_root;
1152 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1154 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1158 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1159 &fops_rtl8366_regs);
1161 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1165 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1166 &fops_rtl8366_vlan);
1168 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1173 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1174 &fops_rtl8366_mibs);
1176 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1182 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1184 if (smi->debugfs_root) {
1185 debugfs_remove_recursive(smi->debugfs_root);
1186 smi->debugfs_root = NULL;
1191 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1192 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1195 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1196 const struct switch_attr *attr,
1197 struct switch_val *val)
1200 struct rtl8366_smi *smi = to_rtl8366(dev);
1202 if (val->value.i == 1) {
1203 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1205 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1211 static int rtl8366_get_vlan(struct switch_dev *dev,
1212 const struct switch_attr *attr,
1213 struct switch_val *val)
1216 struct rtl8366_smi *smi = to_rtl8366(dev);
1218 if (attr->ofs == 1) {
1219 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1221 if (data & RTL8366_CHIP_CTRL_VLAN)
1225 } else if (attr->ofs == 2) {
1226 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1237 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1238 const struct switch_attr *attr,
1239 struct switch_val *val)
1242 struct rtl8366_smi *smi = to_rtl8366(dev);
1243 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1245 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1250 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1251 const struct switch_attr *attr,
1252 struct switch_val *val)
1255 struct rtl8366_smi *smi = to_rtl8366(dev);
1257 if (val->value.i >= 6)
1260 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1262 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1263 data |= val->value.i;
1265 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1270 static int rtl8366_set_vlan(struct switch_dev *dev,
1271 const struct switch_attr *attr,
1272 struct switch_val *val)
1274 struct rtl8366_smi *smi = to_rtl8366(dev);
1277 return rtl8366_vlan_set_vlan(smi, val->value.i);
1279 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1282 static int rtl8366_init_vlan(struct switch_dev *dev,
1283 const struct switch_attr *attr,
1284 struct switch_val *val)
1286 struct rtl8366_smi *smi = to_rtl8366(dev);
1287 return rtl8366s_reset_vlan(smi);
1290 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1291 const struct switch_attr *attr,
1292 struct switch_val *val)
1295 u32 len = 0, data = 0;
1296 int speed, duplex, link, txpause, rxpause, nway;
1297 struct rtl8366_smi *smi = to_rtl8366(dev);
1299 if (val->port_vlan >= RTL8366_NUM_PORTS)
1302 memset(buf, '\0', sizeof(buf));
1303 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1304 (val->port_vlan >> 1),
1307 if (val->port_vlan & 0x1)
1310 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1311 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1312 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1313 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1314 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1315 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1317 len += snprintf(buf + len, sizeof(buf) - len, "Port %d: ",
1321 len += snprintf(buf + len, sizeof(buf) - len,
1322 "Link UP, Speed: ");
1324 len += snprintf(buf + len, sizeof(buf) - len,
1325 "Link DOWN, Speed: ");
1328 len += snprintf(buf + len, sizeof(buf) - len, "10Base-TX ");
1329 else if (speed == 1)
1330 len += snprintf(buf + len, sizeof(buf) - len, "100Base-TX ");
1331 else if (speed == 2)
1332 len += snprintf(buf + len, sizeof(buf) - len, "1000Base-TX ");
1335 len += snprintf(buf + len, sizeof(buf) - len, "Full-Duplex, ");
1337 len += snprintf(buf + len, sizeof(buf) - len, "Half-Duplex, ");
1340 len += snprintf(buf + len, sizeof(buf) - len, "TX-Pause ");
1342 len += snprintf(buf + len, sizeof(buf) - len, "RX-Pause ");
1344 len += snprintf(buf + len, sizeof(buf) - len, "nway ");
1352 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1353 const struct switch_attr *attr,
1354 struct switch_val *val)
1359 struct rtl8366s_vlanconfig vlanMC;
1360 struct rtl8366s_vlan4kentry vlan4K;
1361 struct rtl8366_smi *smi = to_rtl8366(dev);
1363 if (val->port_vlan >= RTL8366_NUM_PORTS)
1366 memset(buf, '\0', sizeof(buf));
1368 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1369 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1371 len += snprintf(buf + len, sizeof(buf) - len, "VLAN %d: Ports: ",
1374 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1376 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1377 index == val->port_vlan)
1378 len += snprintf(buf + len, sizeof(buf) - len, "%d", i);
1380 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1382 len += snprintf(buf + len, sizeof(buf) - len,
1383 "\t\t vid \t prio \t member \t untag \t fid\n");
1384 len += snprintf(buf + len, sizeof(buf) - len, "\tMC:\t");
1385 len += snprintf(buf + len, sizeof(buf) - len,
1386 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1387 vlanMC.vid, vlanMC.priority, vlanMC.member,
1388 vlanMC.untag, vlanMC.fid);
1389 len += snprintf(buf + len, sizeof(buf) - len, "\t4K:\t");
1390 len += snprintf(buf + len, sizeof(buf) - len,
1391 "%d \t \t 0x%04x \t 0x%04x \t %d",
1392 vlan4K.vid, vlan4K.member, vlan4K.untag, vlan4K.fid);
1400 static int rtl8366_set_port_led(struct switch_dev *dev,
1401 const struct switch_attr *attr,
1402 struct switch_val *val)
1405 struct rtl8366_smi *smi = to_rtl8366(dev);
1406 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1407 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1410 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1411 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1412 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1413 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1415 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1416 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1417 (val->value.i << (val->port_vlan * 4));
1418 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1424 static int rtl8366_get_port_led(struct switch_dev *dev,
1425 const struct switch_attr *attr,
1426 struct switch_val *val)
1429 struct rtl8366_smi *smi = to_rtl8366(dev);
1430 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1433 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1434 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1439 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1440 const struct switch_attr *attr,
1441 struct switch_val *val)
1444 struct rtl8366_smi *smi = to_rtl8366(dev);
1445 if (val->port_vlan >= RTL8366_NUM_PORTS)
1448 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1449 data |= (1 << (val->port_vlan + 3));
1450 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1455 static int rtl8366_get_port_mib(struct switch_dev *dev,
1456 const struct switch_attr *attr,
1457 struct switch_val *val)
1461 unsigned long long counter = 0;
1462 struct rtl8366_smi *smi = to_rtl8366(dev);
1463 if (val->port_vlan >= RTL8366_NUM_PORTS)
1466 len += snprintf(buf + len, sizeof(buf) - len, "Port %d MIB counters\n",
1468 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1470 len += snprintf(buf + len, sizeof(buf) - len,
1471 "%d:%s\t", i, MIBCOUNTERS[i]);
1472 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1473 len += snprintf(buf + len, sizeof(buf) - len,
1474 "[%llu]\n", counter);
1476 len += snprintf(buf + len, sizeof(buf) - len,
1485 static int rtl8366_set_member(struct switch_dev *dev,
1486 const struct switch_attr *attr,
1487 struct switch_val *val)
1489 struct rtl8366s_vlanconfig vlanMC;
1490 struct rtl8366s_vlan4kentry vlan4K;
1491 struct rtl8366_smi *smi = to_rtl8366(dev);
1493 if (val->port_vlan >= RTL8366_NUM_VLANS)
1496 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1498 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1500 vlan4K.member = vlanMC.member = val->value.i;
1501 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanMC);
1502 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
1507 static int rtl8366_get_member(struct switch_dev *dev,
1508 const struct switch_attr *attr,
1509 struct switch_val *val)
1511 struct rtl8366s_vlanconfig vlanMC;
1512 struct rtl8366s_vlan4kentry vlan4K;
1513 struct rtl8366_smi *smi = to_rtl8366(dev);
1515 if (val->port_vlan >= RTL8366_NUM_VLANS)
1518 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1520 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1522 val->value.i = vlanMC.member;
1527 static int rtl8366_set_untag(struct switch_dev *dev,
1528 const struct switch_attr *attr,
1529 struct switch_val *val)
1531 struct rtl8366s_vlanconfig vlanMC;
1532 struct rtl8366s_vlan4kentry vlan4K;
1533 struct rtl8366_smi *smi = to_rtl8366(dev);
1535 if (val->port_vlan >= RTL8366_NUM_VLANS)
1538 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1539 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1541 vlan4K.untag = vlanMC.untag = val->value.i;
1542 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanMC);
1543 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
1548 static int rtl8366_get_untag(struct switch_dev *dev,
1549 const struct switch_attr *attr,
1550 struct switch_val *val)
1552 struct rtl8366s_vlanconfig vlanMC;
1553 struct rtl8366s_vlan4kentry vlan4K;
1554 struct rtl8366_smi *smi = to_rtl8366(dev);
1556 if (val->port_vlan >= RTL8366_NUM_VLANS)
1559 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1560 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1563 val->value.i = vlanMC.untag;
1568 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1570 struct rtl8366_smi *smi = to_rtl8366(dev);
1571 return rtl8366_get_vlan_port_pvid(smi, port, val);
1574 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1576 struct rtl8366_smi *smi = to_rtl8366(dev);
1577 return rtl8366_set_vlan_port_pvid(smi, port, val);
1580 static int rtl8366_reset_switch(struct switch_dev *dev)
1582 struct rtl8366_smi *smi = to_rtl8366(dev);
1583 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1584 RTL8366_CHIP_CTRL_RESET_HW);
1588 static struct switch_attr rtl8366_globals[] = {
1590 .type = SWITCH_TYPE_INT,
1591 .name = "enable_vlan",
1592 .description = "Enable VLAN mode",
1593 .set = rtl8366_set_vlan,
1594 .get = rtl8366_get_vlan,
1599 .type = SWITCH_TYPE_INT,
1600 .name = "enable_vlan4k",
1601 .description = "Enable VLAN 4K mode",
1602 .set = rtl8366_set_vlan,
1603 .get = rtl8366_get_vlan,
1608 .type = SWITCH_TYPE_INT,
1609 .name = "init_vlan",
1610 .description = "Initialize VLAN tables to defaults",
1611 .set = rtl8366_init_vlan,
1617 .type = SWITCH_TYPE_INT,
1618 .name = "reset_mibs",
1619 .description = "Reset all MIB counters",
1620 .set = rtl8366_global_reset_mibs,
1625 .type = SWITCH_TYPE_INT,
1626 .name = "blinkrate",
1627 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1628 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1629 .set = rtl8366_global_set_blinkrate,
1630 .get = rtl8366_global_get_blinkrate,
1635 static struct switch_attr rtl8366_port[] = {
1637 .type = SWITCH_TYPE_STRING,
1639 .description = "Get port link information",
1642 .get = rtl8366_attr_get_port_link
1645 .type = SWITCH_TYPE_INT,
1646 .name = "reset_mib",
1647 .description = "Reset single port MIB counters",
1649 .set = rtl8366_reset_port_mibs,
1653 .type = SWITCH_TYPE_STRING,
1655 .description = "Get MIB counters for port",
1658 .get = rtl8366_get_port_mib
1661 .type = SWITCH_TYPE_INT,
1663 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1665 .set = rtl8366_set_port_led,
1666 .get = rtl8366_get_port_led
1670 static struct switch_attr rtl8366_vlan[] = {
1672 .type = SWITCH_TYPE_INT,
1674 .description = "Get/Set VLAN untag port set (bitmask)",
1675 .set = rtl8366_set_untag,
1676 .get = rtl8366_get_untag,
1680 .type = SWITCH_TYPE_INT,
1682 .description = "Get/Set VLAN member port set (bitmask)",
1683 .set = rtl8366_set_member,
1684 .get = rtl8366_get_member,
1688 .type = SWITCH_TYPE_STRING,
1690 .description = "Get vlan information",
1693 .get = rtl8366_attr_get_vlan_info
1699 static struct switch_dev rtldev = {
1701 .cpu_port = RTL8366_PORT_NUM_CPU,
1702 .ports = RTL8366_NUM_PORTS,
1703 .vlans = RTL8366_NUM_VLANS,
1705 .attr = rtl8366_globals,
1706 .n_attr = ARRAY_SIZE(rtl8366_globals),
1709 .attr = rtl8366_port,
1710 .n_attr = ARRAY_SIZE(rtl8366_port),
1713 .attr = rtl8366_vlan,
1714 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1717 .get_port_pvid = rtl8366_get_port_pvid,
1718 .set_port_pvid = rtl8366_set_port_pvid,
1719 .reset_switch = rtl8366_reset_switch,
1722 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1724 struct rtl8366_smi *smi = bus->priv;
1728 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1735 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1738 struct rtl8366_smi *smi = bus->priv;
1742 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1744 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1749 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1754 smi->mii_bus = mdiobus_alloc();
1755 if (smi->mii_bus == NULL) {
1760 spin_lock_init(&smi->lock);
1761 smi->mii_bus->priv = (void *) smi;
1762 smi->mii_bus->name = "rtl8366-smi";
1763 smi->mii_bus->read = rtl8366_smi_mii_read;
1764 smi->mii_bus->write = rtl8366_smi_mii_write;
1765 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1766 dev_name(&smi->pdev->dev));
1767 smi->mii_bus->parent = &smi->pdev->dev;
1768 smi->mii_bus->phy_mask = ~(0x1f);
1769 smi->mii_bus->irq = smi->mii_irq;
1770 for (i = 0; i < PHY_MAX_ADDR; i++)
1771 smi->mii_irq[i] = PHY_POLL;
1773 ret = mdiobus_register(smi->mii_bus);
1780 mdiobus_free(smi->mii_bus);
1785 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1787 mdiobus_unregister(smi->mii_bus);
1788 mdiobus_free(smi->mii_bus);
1791 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1797 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1799 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1804 case RTL8366S_CHIP_ID_8366:
1807 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1811 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1814 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1818 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1819 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1821 rtl8366_debugfs_init(smi);
1826 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1828 static int rtl8366_smi_version_printed;
1829 struct rtl8366_smi_platform_data *pdata;
1830 struct rtl8366_smi *smi;
1833 if (!rtl8366_smi_version_printed++)
1834 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1835 " version " RTL8366_SMI_DRIVER_VER"\n");
1837 pdata = pdev->dev.platform_data;
1839 dev_err(&pdev->dev, "no platform data specified\n");
1844 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1846 dev_err(&pdev->dev, "no memory for private data\n");
1851 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1853 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1854 pdata->gpio_sda, err);
1858 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1860 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1861 pdata->gpio_sck, err);
1867 spin_lock_init(&smi->lock);
1869 platform_set_drvdata(pdev, smi);
1871 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1872 pdata->gpio_sda, pdata->gpio_sck);
1874 err = rtl8366_smi_setup(smi);
1876 goto err_clear_drvdata;
1878 err = rtl8366_smi_mii_init(smi);
1880 goto err_clear_drvdata;
1885 platform_set_drvdata(pdev, NULL);
1886 gpio_free(pdata->gpio_sck);
1888 gpio_free(pdata->gpio_sda);
1895 int rtl8366_phy_config_init(struct phy_device *phydev)
1898 struct net_device *netdev = phydev->attached_dev;
1899 struct rtl8366_smi *smi = phydev->bus->priv;
1900 struct switch_dev *dev = &smi->dev;
1902 /* Only init the switch for the primary PHY */
1903 if (phydev->addr != 4) {
1904 printk(KERN_INFO "Discarding address: %d\n", phydev->addr);
1908 memcpy(&smi->dev, &rtldev, sizeof(struct switch_dev));
1910 dev->netdev = netdev;
1912 err = register_switch(dev, netdev);
1914 printk(KERN_INFO "Switch registration failed\n");
1921 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1926 static struct phy_driver rtl8366_smi_phy_driver = {
1927 .phy_id = 0x001cc960,
1928 .name = "Realtek RTL8366",
1929 .phy_id_mask = 0x1ffffff0,
1930 .features = PHY_GBIT_FEATURES,
1931 .config_aneg = rtl8366_phy_config_aneg,
1932 .config_init = rtl8366_phy_config_init,
1933 .read_status = genphy_read_status,
1935 .owner = THIS_MODULE,
1939 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1941 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1944 struct rtl8366_smi_platform_data *pdata;
1946 pdata = pdev->dev.platform_data;
1948 rtl8366_debugfs_remove(smi);
1949 phy_driver_unregister(&rtl8366_smi_phy_driver);
1950 rtl8366_smi_mii_cleanup(smi);
1951 platform_set_drvdata(pdev, NULL);
1952 gpio_free(pdata->gpio_sck);
1953 gpio_free(pdata->gpio_sda);
1960 static struct platform_driver rtl8366_smi_driver = {
1962 .name = RTL8366_SMI_DRIVER_NAME,
1963 .owner = THIS_MODULE,
1965 .probe = rtl8366_smi_probe,
1966 .remove = __devexit_p(rtl8366_smi_remove),
1969 static int __init rtl8366_smi_init(void)
1972 ret = platform_driver_register(&rtl8366_smi_driver);
1976 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1978 goto err_platform_unregister;
1982 err_platform_unregister:
1983 platform_driver_unregister(&rtl8366_smi_driver);
1986 module_init(rtl8366_smi_init);
1988 static void __exit rtl8366_smi_exit(void)
1990 phy_driver_unregister(&rtl8366_smi_phy_driver);
1991 platform_driver_unregister(&rtl8366_smi_driver);
1993 module_exit(rtl8366_smi_exit);
1995 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1996 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1997 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1998 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1999 MODULE_LICENSE("GPL v2");
2000 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);